IC Floorplanning With In-Die Stitching Filler Rows
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Solution Overview
Problem
The complexity of at-resolution stitching in high-NA EUVL scanners requires nanometer-order precision for optical proximity correction and overlay control, which is challenging to achieve in IC devices with die sizes exceeding the exposure field.
Innovation Solution
Incorporating an in-die stitching sub-region with filler cells having a critical dimension greater than the adjacent circuit cells, allowing for relaxed precision requirements during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If in-die stitching is performed at EUVL resolution, then the die size can exceed the exposure field, but the manufacturing precision requirement increases to nanometer-order precision for optical proximity correction and overlay control
Solution Approach 1:
The patent introduces a stitching region as an intermediary zone between two separately exposed regions. This stitching region contains stitching markers that facilitate precise alignment and overlay control during the stitching process, acting as a mediator that enables accurate joining of the two image fields without requiring nanometer-order precision across the entire die.
Solution Approach 2:
The patent divides the die into two separately exposed regions that are stitched together. By segmenting the exposure process into two distinct fields with a dedicated stitching region in between, the complex task of maintaining nanometer-order precision across the entire large die is broken down into more manageable alignment tasks localized to the stitching region.
2Area of stationary object
If in-die stitching is performed at EUVL resolution, then the die size can exceed the exposure field, but the device complexity increases due to stitching specific design rules and optical proximity correction
Solution Approach 1:
The stitching region serves as an intermediary that contains all the complexity of stitching-specific design rules and optical proximity correction. By localizing these complex requirements to a dedicated stitching region rather than applying them across the entire die, the overall device complexity is managed more effectively while still enabling large die sizes.
Solution Approach 2:
The patent applies stitching-specific design rules and optical proximity correction locally to the stitching region rather than uniformly across the entire die. This localized approach reduces the overall device complexity by limiting the application of complex design constraints to only where they are needed for successful stitching.
3Quantity of substance
If the in-die stitching sub-region uses the same critical dimension as adjacent circuit cells, then the feature density is maintained, but the alignment precision requirement increases
Solution Approach 1:
The patent applies different critical dimension requirements to different regions: the stitching region uses a relaxed critical dimension while adjacent circuit cells maintain their original critical dimensions. This local differentiation allows the stitching region to have lower alignment precision requirements while still maintaining overall feature density across the die.
Data Source
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AI summary
In an aspect there is provided an IC device comprising: a die; a circuit region extending along the die in first and second transverse directions and comprising a plurality of circuit cells arranged in a plurality of rows extending in parallel in the first direction; wherein the circuit region comprises a first sub-region comprising a first sub-set of the plurality of rows of circuit cells, a second sub-region comprising a second sub-set of the plurality of rows of circuit cells, and an in-die stitching sub-region extending across the circuit region in the first direction, wherein the first and second sub-regions are arranged on opposite sides of the in-die stitching sub-region, and wherein the in-die stitching sub-region is formed by a third sub-set of one or more rows of the plurality of rows of circuit cells, wherein the circuit cells of the third sub-set are configured as filler cells with a critical dimension which is greater than a corresponding critical dimension of the circuit cells of the first and second sub-sets. There is further provided a method for floorplanning of a circuit region of an IC device.