IC Force Mitigation System for Under-Pad Wire Bond Damage
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Solution Overview
Problem
Integrated circuit (IC) devices face under-pad damage due to wire bonding, which introduces significant stresses and cracks in semiconductor components, limiting the formation of certain types of components below bond pads, especially as silicon die size decreases.
Innovation Solution
A force mitigation system is implemented in IC devices, featuring a metal shock plate and an array of sealed voids between the shock plate and a sealing layer, which reduces stress by creating a void cushion and mitigating damage from wire bonding and passivation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is performed to connect silicon chip to leads, then electrical connection is achieved, but large stresses and cracks are introduced in the chip below bond pads
Solution Approach 1:
A force mitigation layer is introduced as an intermediary structure between the bond pad and the underlying semiconductor components. This layer includes an array of sealed voids that act as a cushion to absorb and distribute the mechanical stress from wire bonding, preventing direct transmission of forces to sensitive devices below the pad
Solution Approach 2:
The force mitigation layer changes the mechanical parameters of the structure by introducing compliant void spaces. These voids allow local deformation and stress distribution, transforming the rigid structure into a more compliant system that can accommodate bonding forces without causing damage to underlying components
2Object-affected harmful factors
If solid metal plates are formed in die body for absorbing forces, then under-pad damage is reduced, but additional metal layers reduce usable real estate area
Solution Approach 1:
The force mitigation layer employs a porous structure with an array of sealed voids instead of solid metal plates. This porous configuration provides mechanical compliance for stress absorption while occupying minimal space, as the voids themselves are the functional element rather than requiring additional solid material layers
Solution Approach 2:
The force mitigation structure is formed within the existing dielectric layer thickness rather than adding horizontal layers. The array of sealed voids utilizes the vertical dimension within the dielectric stack, allowing force mitigation functionality without expanding the lateral footprint and preserving usable chip area
3Object-affected harmful factors
If interlaced patterns of metal and dielectric are formed for mitigating under-pad damage, then stress is reduced, but additional dielectric layers reduce usable real estate area
Solution Approach 1:
The force mitigation layer uses a porous dielectric structure with sealed voids instead of interlaced metal-dielectric patterns. This approach achieves stress mitigation through the compliant void spaces within a single dielectric layer, eliminating the need for multiple alternating layers and associated complexity
Data Source
AI summary
An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.