IC Gate Height Control via Masked Recessing
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Solution Overview
Problem
Current IC fabrication techniques face challenges in controlling gate height, particularly for short channel gate structures, as they tend to have limited minimum gate height due to over-polishing during planarization, leading to performance limitations and reduced yield.
Innovation Solution
The method involves forming a long channel gate structure and a short channel gate structure with a mask over the short channel gate structure to recess the gate material, ensuring the short channel gate structure's gate height is no larger than the long channel gate structure's, thereby avoiding over-polishing and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a planarization process is used to remove gate material over long channel gate structures, then the gate height of long channel gate structures is reduced, but the gate height of short channel gate structures is过度 reduced (over-polished), resulting in shorter gates than desired
Solution Approach 1:
The patent applies different gate heights to different channel lengths: long channel gate structures have a first gate height while short channel gate structures have a second gate height that is less than the first gate height. This local differentiation resolves the contradiction by allowing each structure type to have the optimal gate height for its specific channel length, preventing over-polishing of short channel structures while still reducing height where needed for long channel structures.
2Manufacturing precision
If additional planarization is applied to reduce the average gate height, then the overall gate height is reduced, but some regions are over-polished, lowering yield
Solution Approach 1:
The patent performs preliminary differentiation of gate heights before the final planarization process. By forming long channel gate structures with a first gate height and short channel gate structures with a second gate height (less than the first) in advance, the subsequent planarization process can be controlled to avoid over-polishing. This preliminary action ensures that short channel structures start at the correct height, preventing yield loss from over-processing.
Data Source
AI summary
An integrated circuit (IC) structure includes a long channel (LC) gate structure over a long channel region, the LC gate structure having a first gate height; and a short channel (SC) gate structure over a short channel region, the SC gate structure having a second gate height. The short channel region is shorter in length than the long channel region. The second gate height of the SC gate structure is no larger than the first gate height of the LC gate structure.