Integrated Circuit Gate Protection During Metallization

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Solution Overview

Problem

The scaling down of gate oxides in semiconductor devices leads to charge buildup during physical vapor deposition, causing damage to transistors and reducing yield, as conventional reverse bias diodes are costly and inefficient in managing charge discharge.

Innovation Solution

A transistor configured to switch ON and discharge accumulated charges on an interconnect line during metallization, using a coupling capacitor to protect coupled transistors, with the transistor's gate remaining floating until grounded at the topmost metal level, replacing the need for multiple diodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reverse bias diodes are used to protect gates from charge buildup, then gate protection is provided, but device area, power consumption, and signal propagation delay increase

Engineering Contradiction:
Improvegate protectionVSAvoidnumber of diodes
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention merges the protection function with the interconnect structure itself by creating an antenna diode where the interconnect line forms one electrode of the diode structure. This eliminates the need for separate discrete diode components while maintaining gate protection functionality during PVD processing.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interconnect line serves dual purposes: it functions as both the electrical connection for signal transmission and as the cathode electrode of the antenna diode for charge protection. This multi-functionality reduces the overall component count and device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple diodes are placed on interconnect lines to protect gates, then charge discharge capability is improved, but area and power consumption increase

Engineering Contradiction:
Improvecharge discharge capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention extracts the protective diode structure from being a separate component and integrates it directly into the interconnect line itself. The interconnect line becomes part of the diode structure, eliminating the need for additional discrete diode components that would occupy extra device area.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The protection function is merged with the interconnect structure by forming the antenna diode using the interconnect line as one electrode. This integration eliminates the need for separate diode components and reduces the overall area required for protection structures.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If reverse bias diodes are used for gate protection, then charge buildup is prevented, but signal propagation delay increases

Engineering Contradiction:
Improvecharge buildup preventionVSAvoidsignal propagation delay
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The invention merges the protection function with the interconnect structure itself by creating an antenna diode where the interconnect line forms one electrode of the diode structure. This eliminates the need for separate discrete diodes per interconnect line, thereby reducing the capacitive loading and associated signal propagation delays.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If conventional diodes are used to discharge accumulated charge, then gate protection is achieved, but current carrying capacity is limited

Engineering Contradiction:
Improvegate protectionVSAvoidcurrent carrying capacity
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The invention merges the protection function with the interconnect structure itself by creating an antenna diode where the interconnect line forms one electrode of the diode structure. This eliminates the need for separate discrete diodes per interconnect line, thereby reducing the capacitive loading and associated signal propagation delays.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively prevents charge buildup, reducing area, current leakage, and signal delay while providing superior current carrying capacity compared to conventional diodes, enhancing transistor reliability and manufacturing yield.

Implementation Method 1

The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

physical vapor deposition (PVD, also known as sputtering) is commonly used to deposit thin films of metal on a silicon substrate

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 3

This process involves conversion of target material into vapor phase by ion bombardment

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 4

A plasma or glow discharge is an energetic ionized gas generated by electric discharge in a gaseous medium

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 5

A plasma or glow discharge is an energetic ionized gas generated by electric discharge in a gaseous medium

Methodology Applied
Scientific EffectElectric discharge: Electric Arc

Data Source

PatentUS8264043B1Protection of integrated circuit gates during metallization processes
Publication Date: 2012.09.11 CYPRESS SEMICONDUCTOR CORP
  • US8264043B1 patent drawing
  • US8264043B1 patent drawing
  • US8264043B1 patent drawing

AI summary

In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.