IC Gate Resistance Modeling for Accurate Layout Netlists
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Solution Overview
Problem
Existing gate resistance modeling methods in integrated circuit (IC) design underestimate the actual resistance values, leading to inaccuracies in design and manufacturing processes.
Innovation Solution
Incorporating a second modeled gate resistance value and adding a resistor at the terminal node to update the netlist, thereby increasing the accuracy of gate resistance modeling by accounting for additional gate via positions and configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing gate resistance modeling methods are used, then the design process is simple and fast, but the resistance values are underestimated and accuracy is poor
Solution Approach 1:
The gate resistance is segmented into multiple components: access resistance (Raccess) from source/drain regions, gate electrode resistance (Rgate), and interconnect resistance (Rinterconnect). This segmentation allows each resistance component to be modeled separately with appropriate geometric parameters and material properties, improving overall accuracy while maintaining manageable complexity through modular calculation.
Solution Approach 2:
Different regions of the gate structure are assigned different resistance characteristics based on their local properties. The access resistance varies with source/drain region geometry, the gate electrode resistance depends on gate material and dimensions, and the interconnect resistance accounts for via and contact hole configurations. This local quality approach enables precise modeling of each region's contribution to total gate resistance.
2Reliability
If existing gate resistance modeling methods are used, then the computational process is fast, but the design specifications compliance is compromised
Solution Approach 1:
Resistivity values for different materials (polysilicon, copper, tungsten, aluminum) are pre-calculated and stored based on standard process parameters. Geometric factors are pre-determined from layout data. This preliminary preparation allows the final gate resistance calculation to quickly combine these pre-computed values with device-specific dimensions, ensuring specification compliance without excessive computational time during the actual design process.
3Measurement precision
If traditional resistance modeling is used, then the netlist is simple, but the performance prediction is inaccurate
Solution Approach 1:
The netlist integrates multiple resistance components (Raccess, Rgate, Rinterconnect) into a unified gate resistance model that accurately reflects the total resistance from source to drain through the gate. This merging of separate resistance elements into a comprehensive model improves performance prediction accuracy while the automated calculation methods keep the netlist management tractable through systematic parameter organization.
Data Source
AI summary
An IC device design system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs, the storage medium and the code being configured to, with the processor, cause the system to receive an IC device layout diagram including a gate region having a width extending at least from a first edge of an active region to a second edge of the active region and a gate via at a location within the active region and along the width, receive a first gate resistance value corresponding to the gate region, retrieve a second gate resistance value from a resistance value reference based on the location and the width, and based on the second gate resistance value being greater than the first gate resistance value, add a gate terminal node and a resistor to a netlist corresponding to the gate region.