Non-Uniform Polysilicon Gate Width Adjustment for IC Parameter Uniformity
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Solution Overview
Problem
Integrated circuit manufacturing processes result in non-uniform device performance across a chip due to variations in device parameters, leading to inconsistent performance of identically designed devices fabricated in different regions.
Innovation Solution
A method involving the measurement of test device parameters on one wafer and adjusting the physical polysilicon gate widths or source/drain ion implantation steps of field effect transistors on another wafer to achieve uniform functional device parameters across regions, by applying non-uniform adjustments based on measured values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard manufacturing processes are used, then production efficiency is maintained, but device parameter uniformity across chip regions deteriorates
Solution Approach 1:
The patent applies preliminary action by measuring test device parameters on a first wafer before manufacturing field effect transistors on a second wafer. The measured values from the first wafer are used to pre-determine the non-uniform adjustment values that will be applied to different regions of the second wafer, allowing process optimization to be prepared in advance rather than requiring real-time adjustments during fabrication.
Solution Approach 2:
The patent implements local quality by applying different non-uniform adjustment values to different regions of the wafer based on measured parameter variations. Instead of using a uniform adjustment across the entire wafer, the method tailors the adjustment to each specific region's characteristics, thereby improving device parameter uniformity locally across different chip regions.
2Manufacturing precision
If uniform physical dimensions are used across all regions, then manufacturing simplicity is maintained, but functional parameter uniformity deteriorates due to process variations
Solution Approach 1:
The patent applies parameter changes by intentionally varying the physical polysilicon gate widths or source/drain ion implantation parameters across different regions of the wafer. These physical parameter variations are designed to compensate for process-induced variations, transforming the uniform physical design into a non-uniform physical implementation that achieves uniform functional outcomes.
Solution Approach 2:
The patent employs inversion by reversing the conventional approach: instead of making physical dimensions uniform to achieve functional uniformity, it deliberately creates non-uniform physical dimensions to compensate for process variations and achieve functional uniformity. This inverts the traditional design philosophy of uniformity.
3Manufacturing precision
If region-specific adjustments are applied, then device parameter uniformity improves, but process complexity increases
Solution Approach 1:
The patent implements feedback by measuring actual test device parameter values on a first wafer and using these measured values to determine the non-uniform adjustment values applied to subsequent wafers. This closed-loop feedback mechanism allows the process to self-correct for variations, using actual measurement data to guide the compensation strategy rather than relying on theoretical models.
Solution Approach 2:
The patent applies copying by using the measured parameter values and determined adjustment values from a first wafer (which may be a test or pilot wafer) and applying the same non-uniform adjustment pattern to subsequent production wafers. This allows the optimization determined from one wafer to be replicated and applied consistently across multiple production wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces within-chip device parameter variations, ensuring that identically designed transistors in different regions of an integrated circuit chip exhibit the same functional parameters, thereby enhancing the uniformity and performance of integrated circuit chips.
Implementation Method 1
adjusting a same functional device parameter of identically designed field effect transistors within one or more same regions of all integrated circuit chips of the second wafer based on a values of the same test device parameter measured on test devices in regions of the integrated circuit chip of the first wafer corresponding to the one or more same regions of the integrated circuit chips of the second wafer by a non-uniform adjustment of physical source/drain ion implantation fabrication steps
Data Source
AI summary
A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.