Glitch Detection in ICs via Floating Point Analysis
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Solution Overview
Problem
Existing methods for detecting glitches in integrated circuits are time-consuming and inefficient, requiring extensive signal feeding and observation of all possible input signal changes to identify false output results.
Innovation Solution
A glitch occurring point detection apparatus and method that uses a processing circuit and memory to perform DC analysis on internal circuit nodes, identifying candidate floating points without charging or discharging paths, and determining these points as glitch occurring points by backtracking from the output node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all possible groups of input signals are fed to the under-test circuit based on different orders to obtain comprehensive observation, then the detection completeness is improved, but the detection time increases significantly
Solution Approach 1:
The patent extracts and focuses on a specific subset of critical nodes (floating points without charging/discharging paths) from the entire circuit, rather than observing all nodes. This extraction allows comprehensive glitch detection at critical points without the need to feed all possible input signal combinations, thereby reducing detection time while maintaining detection effectiveness
Solution Approach 2:
The patent performs preliminary DC analysis to identify candidate floating points before conducting the actual glitch detection. By pre-identifying the critical nodes that are most likely to exhibit glitches, the method prepares the detection framework in advance, avoiding the need for exhaustive signal feeding during the actual detection phase
2Productivity
If DC analysis is performed on internal circuit nodes to retrieve candidate floating points, then the detection efficiency is improved, but the analysis complexity increases
Solution Approach 1:
The patent applies DC analysis selectively to identify specific local characteristics (floating points) rather than performing comprehensive analysis on the entire circuit. By focusing on nodes without charging or discharging paths, the method achieves efficient glitch detection with reduced analysis complexity compared to exhaustive circuit analysis
Data Source
AI summary
The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.