Integrated Circuit Ground Contact Pad Removal via Backside Substrate Conduction
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Solution Overview
Problem
In CMOS integrated circuit fabrication, the surface area occupied by contact pads is significant, limiting the density of integrated circuits on a semiconductor wafer due to the necessity of ground pads both on the front and back sides, which cannot be reduced by existing singulation and connection techniques.
Innovation Solution
The method involves embedding a ground contact pad within a scribe line on the semiconductor wafer, allowing it to be destroyed during singulation, and replacing it with a backside ground contact, utilizing the low series resistance between the substrate and circuit region to apply ground potential, thus reducing the surface area occupied by contact pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ground contact pad is provided on the front side of the integrated circuit, then the electrical connection to ground is ensured, but the surface area occupied by contact pads increases
Solution Approach 1:
The ground contact function is moved from the front side (two-dimensional plane) to the back side of the substrate, utilizing the third dimension (depth/vertical arrangement) to resolve the space conflict. The ground contact pad is positioned in a scribe line on the front side and electrically connected to a ground contact on the back side, effectively moving the ground connection function to another dimension.
Solution Approach 2:
The ground contact function is extracted from the front side contact pad area and separated into a distinct back side contact. This extraction removes the ground connection requirement from the front side layout, allowing the ground contact pad to be placed in a scribe line where it does not occupy valuable circuit area.
2Productivity
If the surface area of contact pads is reduced, then the density of integrated circuits on the wafer increases, but the electrical connection reliability may be compromised
Solution Approach 1:
By moving the ground contact to the back side of the substrate, the invention frees up front side surface area for additional circuits while maintaining electrical connection reliability through the substrate's internal conductivity. This dimensional relocation allows higher circuit density without compromising connection quality.
Solution Approach 2:
The substrate itself serves as the electrical connection medium between the front side ground contact pad and the back side ground contact. The substrate's inherent conductivity provides the electrical path, eliminating the need for additional external connection structures and enabling area reduction.
3Area of moving object
If the ground contact pad is placed in a scribe line, then the usable circuit area is maximized, but the ground contact pad may be damaged during singulation
Solution Approach 1:
The ground contact function is segmented into two separate locations: a small ground contact pad in the scribe line on the front side and a larger ground contact on the back side. This segmentation allows the front side pad to be minimal (maximizing circuit area) while the back side contact provides robust electrical connection that survives singulation.
Solution Approach 2:
The critical ground connection function is relocated to the back side dimension, where it is protected from singulation damage. The front side scribe line pad serves only as an electrical interface, while the actual ground connection is established on the back side where it can tolerate the singulation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall size of the integrated circuit, enabling a higher density of circuits on a given wafer surface area by eliminating the need for a front-side ground pad and allowing the backside to serve as the ground contact post-singulation.
Implementation Method 1
substrate 10 can be electrically linked with a very low series resistance to circuit region 11, by the intermediary of internal connections in doped silicon
Data Source
AI summary
The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.