3D Interleaved Loop IC Inductor Design
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Solution Overview
Problem
Existing integrated circuit (IC) inductor designs face limitations in achieving high inductance while minimizing chip space, particularly in multi-layer ICs, as they often rely on two-dimensional spiral traces or limited three-dimensional configurations.
Innovation Solution
The development of a three-dimensional inductive device with interleaved loops and interconnect segments across multiple conductive layers, utilizing jumpers and vias to connect loops between layers, forming high inductance coils that extend over multiple layers without occupying excessive space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional two-dimensional spiral traces are used, then the device structure is simple, but the inductance value is limited and chip area occupation is large
Solution Approach 1:
The patent transitions from two-dimensional spiral traces to three-dimensional interleaved loop structures across multiple conductive layers. The inductor utilizes alternating conductive and insulating layers with vertical vias to create a multi-layer configuration, effectively adding the vertical dimension to increase inductance density without proportionally increasing chip area.
Solution Approach 2:
The patent implements nested loop structures where inner loops are contained within outer loops across multiple layers. The interleaved configuration of first and second loops with shared interconnect segments creates a compact nested arrangement that maximizes inductance within the available space.
2Quantity of substance
If more conductive layers are used to increase inductance, then the inductance value improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the inductor structure into segmented loops distributed across multiple conductive layers. Each layer contains discrete loop segments that are interconnected through vias, allowing the inductor to achieve high inductance through modular segmentation rather than a single complex continuous structure.
Solution Approach 2:
The patent combines multiple loop structures across different conductive layers into a unified interleaved configuration. The first and second loops from different layers are merged through shared interconnect segments and vias, creating an integrated multi-layer inductor that achieves high inductance while managing structural complexity.
3Reliability
If continuous vias are used to interconnect metal layers, then the Q factor improves for high frequency applications, but the manufacturing process becomes more complex
Solution Approach 1:
The patent incorporates via structures as integral parts of the layer deposition process, forming conductive pathways between layers during the standard multi-layer fabrication sequence. The vias are prepared and filled as preliminary steps before the final trace patterns are deposited, integrating the interconnection process into the existing manufacturing flow rather than adding separate complex steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the creation of high inductance IC inductors that occupy minimal chip area, effectively addressing the limitations of traditional designs by utilizing multiple layers with alternating conductive and insulating layers and interconnects.
Implementation Method 1
traces in a first and second of the conductive layers form a respective pair of interleaved loops
Data Source
AI summary
An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.