Integrated Circuit Instruction Scheduler for Power Throughput Trade-off
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Solution Overview
Problem
The reduction in feature sizes of integrated circuits (ICs) leads to increased power dissipation challenges, making it difficult to further miniaturize them while maintaining throughput performance, as traditional design paradigms like instruction level parallelism are not suitable for miniaturized ICs, and dynamic voltage and frequency scheduling (DVFS) negatively impacts throughput in power-sensitive domains.
Innovation Solution
An integrated circuit with a first data processing unit operating at full frequency and multiple second data processing units operating at reduced frequency, where instructions are scheduled based on data dependencies to ensure dependent instructions are executed serially at full frequency and independent instructions are executed in parallel at reduced frequency, maintaining throughput while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instruction level parallelism is used to increase throughput, then processing speed is improved, but power dissipation increases making further miniaturization difficult
Solution Approach 1:
The processor is segmented into multiple execution units (first execution unit and second execution units), where the first execution unit handles dependent instructions and second execution units handle independent instructions. This segmentation allows parallel processing of independent instructions while maintaining sequential processing of dependent instructions, achieving throughput improvement without proportional power increase
Solution Approach 2:
The system dynamically schedules instructions to different execution units based on data dependency analysis. The instruction scheduler evaluates dependencies and dynamically assigns instructions to appropriate execution units, enabling adaptive parallelism that improves throughput while controlling power consumption by only parallelizing when necessary
2Use of energy by moving object
If dynamic voltage and frequency scheduling is used to reduce power consumption, then power dissipation is reduced, but throughput performance deteriorates
Solution Approach 1:
The system dynamically adjusts the operational state of different execution units based on instruction characteristics. Independent instructions are assigned to second execution units operating at reduced power, while dependent instructions use the first execution unit at full performance, creating a dynamic power-performance balance that maintains throughput while reducing overall power consumption
Solution Approach 2:
Different execution units are assigned different operational characteristics - the first execution unit is optimized for sequential dependent instruction processing while second execution units are optimized for parallel independent instruction processing. This local differentiation allows the system to match execution unit characteristics to instruction types, maintaining throughput for critical paths while reducing power for parallelizable work
Data Source
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AI summary
Disclosed is an integrated circuit (100) comprising a set of data processing units (120, 130) including a first data processing unit (120) operable at a full operating frequency and N second data processing units (130) operable at a reduced operating frequency in a mode of operation of the IC, wherein N is an integer having a value of at least 2; an instruction scheduler (110) adapted to evaluate data dependencies between individual instructions in a received plurality of instructions to identify dependent instructions in said plurality having said data dependencies and independent instructions in said plurality not having said data dependencies; assign the dependent instructions to the first data processing unit (120) for serial execution on the first data processing unit at the full operating frequency; and assign the independent instructions to the plurality of second data processing units (130) for parallel execution on said second data processing units at the reduced operating frequency. An electronic device comprising such an IC and a method of scheduling instructions for such an IC are also disclosed.