IC Interconnect Repair Using BIST and Redundant Links
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Solution Overview
Problem
The increasing complexity of integrated circuit packaging makes it difficult to detect and repair connection failures efficiently, particularly in 3D and 2.5D integrated circuits, as existing scan-based solutions require long testing times, off-chip repair decisions, and are not adaptable to various designs.
Innovation Solution
A built-in self-test (BIST) approach with redundant interconnects and dedicated repair control circuits, such as TX and RX repair control circuits, is used to identify and fix failed interconnects within integrated circuits, reducing side-band communication and enabling efficient on-chip repair decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If scan-based solutions are used for interconnect testing and repair, then comprehensive detection capability is achieved, but testing time becomes excessively long
Solution Approach 1:
The patent implements built-in self-test (BIST) circuits that are pre-integrated into the interconnect structure, allowing testing to occur automatically without external scan equipment. This preliminary integration of test functionality enables rapid detection of interconnect failures without the time-consuming external scan processes
Solution Approach 2:
The patent replaces mechanical scan-based testing with an electrical BIST system that uses embedded test circuits to generate test patterns and detect failures electrically. This substitution eliminates the need for physical scan chain traversal, dramatically reducing testing time while maintaining detection capability
2Ease of repair
If external repair control is used, then repair decisions can be made, but side-band communication requirements increase system complexity
Solution Approach 1:
The patent implements self-service repair by embedding repair control circuits directly at the interconnect endpoints. These circuits autonomously receive test results from the BIST system and execute repair decisions locally without requiring external control signals, thereby eliminating side-band communication infrastructure
Solution Approach 2:
The patent merges the test control and repair control functions into a single integrated BIST system. By combining detection and repair capabilities in one unified circuit block, the system eliminates the need for separate communication channels between test equipment and repair controllers, reducing overall system complexity
3Ease of manufacture
If generic repair solutions are applied, then implementation is simplified, but adaptability to various circuit designs is reduced
Solution Approach 1:
The patent implements a universal BIST framework that can adapt to different interconnect types (wired-AND, wired-OR, custom logic) through configurable test pattern generation. The same basic BIST architecture serves multiple design scenarios by adjusting its test vectors and evaluation logic, providing both simplicity and adaptability
Data Source
AI summary
Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die transmits a test pattern to the second circuit die via the interconnect layer. Then, the second circuit die determines that a first interconnect has failed based on the test pattern and generates a signature. Finally, the second circuit die uses signatures to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.