Directly Coupled IC Interconnect Layers for Lower PDN IR Drop
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Solution Overview
Problem
As semiconductor device density increases in integrated circuits (ICs), the need for more power and ground connections grows, but conventional power distribution networks (PDNs) face challenges due to increased contact resistance in smaller metal lines, leading to higher current-resistance (IR) drops.
Innovation Solution
The implementation of directly coupled metal lines between vertically-adjacent interconnect layers in the BEOL interconnect structure, eliminating the need for intermediate via layers and reducing contact resistance, thereby minimizing the IR drop and allowing for a more compact IC design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the physical size of metal lines in metallization layers is reduced to increase device density, then device density increases, but contact resistance of metal lines increases
Solution Approach 1:
The patent merges two adjacent metallization layers by eliminating the intermediate via layer, allowing metal lines from both layers to be in direct contact. This combining of layers reduces the number of interfaces and thus reduces contact resistance while maintaining compact device density.
Solution Approach 2:
The patent removes the via layer (intermediate structure) that traditionally couples adjacent metallization layers. By eliminating this intermediary, the metal lines from adjacent layers can directly contact each other, reducing the contact resistance that would otherwise be introduced by the via structure.
2Reliability
If multiple vias are provided to couple adjacent metal lines in adjacent metallization layers, then contact resistance decreases, but device complexity increases
Solution Approach 1:
The patent extracts or removes the via layer from the interconnect structure, eliminating the need for multiple vias to couple adjacent metal lines. This extraction simplifies the interconnect structure while maintaining low contact resistance through direct metal-to-metal contact between adjacent metallization layers.
Solution Approach 2:
By merging adjacent metallization layers and enabling direct metal line contact, the patent eliminates the need for multiple via structures, thereby reducing interconnect complexity while maintaining effective electrical coupling.
3Reliability
If via layers are used to interconnect metal lines in vertically-adjacent interconnect layers, then interconnect reliability is maintained, but the height of the semiconductor die stack increases
Solution Approach 1:
The patent extracts or removes the intermediate via layer from the vertical interconnect stack. By taking out this layer, the overall height of the die stack is reduced while maintaining interconnect reliability through direct metal-to-metal contact between adjacent metallization layers.
Solution Approach 2:
The patent transitions from a three-dimensional via-based vertical interconnect approach to a two-dimensional direct contact approach within the plane of adjacent metallization layers, effectively reducing the vertical dimension (height) of the die stack while maintaining electrical connectivity.
Data Source
AI summary
Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC. An insulating layer(s) can be disposed in select recessed regions between the overlying interconnect layer and the underlying interconnect layer to insulate an overlying metal line from another vertically-intersecting underlying metal line that are not intended to be electrically coupled together.