IC Interconnect Structure With Metal-Free Fault Detection Windows
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Solution Overview
Problem
The increasing complexity of manufacturing integrated circuit (IC) chips due to scaling down has made fault detection challenging, as signals emitted by semiconductor devices are often blocked by metal elements in the interconnect structures, hindering real-time fault detection.
Innovation Solution
Incorporation of metal-free regions in the front-side interconnect structures of IC chips, where fault detection lines are integrated to reduce signal propagation path length and area, allowing for efficient detection of semiconductor device faults by placing detectors outside the metal elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal elements are used in interconnect structures to ensure electrical connectivity, then electrical conductivity is improved, but fault detection capability deteriorates due to signal blocking
Solution Approach 1:
The interconnect structure is segmented into metal-containing regions (for electrical connectivity) and metal-free regions (for fault detection). This spatial segmentation allows simultaneous achievement of electrical conductivity and fault detection capability by assigning different functional requirements to different segments of the interconnect structure.
Solution Approach 2:
Different regions of the interconnect structure have different material compositions: metal elements are placed in regions requiring electrical connectivity, while metal-free regions are created where fault detection signals need to propagate. This local differentiation of material properties resolves the contradiction between conductivity and detectability.
2Difficulty of detecting and measuring
If metal-free regions are created for fault detection, then fault detection capability is improved, but the volume and area of metal-free regions increase
Solution Approach 1:
The fault detection functionality is transitioned from a volumetric metal-free region to a surface-level feature. By placing the metal-free region at the top surface of the interconnect structure and using surface-emitting detectors, the solution reduces the volume of metal-free space while maintaining detection capability through dimensional transformation.
Solution Approach 2:
Instead of creating large volumetric metal-free regions throughout the interconnect structure, the patent uses a surface-level metal-free region that acts as a window or interface for detection. This superficial copy or representation of the metal-free concept suffices for detection purposes without requiring extensive volume removal.
3Speed
If signal propagation path is shortened for efficient fault detection, then detection speed is improved, but the precision of signal emission requirements increases
Solution Approach 1:
The fault detection line itself emits the detection signal, making the interconnect structure self-diagnostic. This self-service approach eliminates the need for external signal sources and complex positioning systems, thereby reducing manufacturing precision requirements while maintaining fast detection speed through the short integrated path.
Data Source
AI summary
An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.