Variable-Dimension IC Interconnect Structure for Better RC Performance
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Solution Overview
Problem
The existing damascene process is unable to effectively pattern metal lines and vias with different dimensions based on the performance characteristics of various circuit blocks in integrated circuits, leading to suboptimal connection performance and increased resistance/capacitance (RC) characteristics due to the requirement for barrier metal layers.
Innovation Solution
An interconnect structure featuring metal lines divided into sections with varying thicknesses and vias with different protrusion heights and widths, where each via is a continuous structure without a connection surface and lacks a barrier metal layer between the vias and the dielectric structure, allowing for customized dimensions to match the performance needs of different circuit blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier metal layers are used to prevent material diffusion, then connection reliability is improved, but resistance/capacitance performance deteriorates and manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the barrier metal layer from the interconnect structure. By eliminating the barrier metal layer that prevents material diffusion, the invention reduces resistance and capacitance values, thereby improving RC characteristic performance while maintaining connection reliability through alternative structural designs.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interconnect structure by removing the barrier metal layer. This parameter change results in lower resistance and capacitance values, improving the overall RC performance of the interconnect structure while maintaining structural integrity through modified material compositions.
2Ease of manufacture
If uniform metal line dimensions are used, then manufacturing simplicity is maintained, but performance characteristics cannot be optimized for different circuit blocks
Solution Approach 1:
The patent applies local quality by creating metal lines with varying thicknesses at different locations. The interconnect structure includes first, second, and third portions with different thicknesses, allowing each region to be optimized for specific circuit block requirements while maintaining a unified manufacturing process flow.
Solution Approach 2:
The patent segments the metal line into multiple portions with different thicknesses. The interconnect structure is divided into first, second, and third portions, each with optimized dimensions tailored to the specific performance requirements of different circuit blocks, enabling localized performance optimization.
3Object-affected harmful factors
If barrier metal layers are included in via structures, then material diffusion is prevented, but available space for conductive material decreases
Solution Approach 1:
The patent extracts and removes the barrier metal layer from the via structure. By eliminating this layer, the invention increases the volume available for conductive material such as copper, thereby improving conductivity and reducing resistance without allowing material diffusion through alternative structural approaches.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
An interconnect structure for an integrated circuit (10) may include: a metal line (M) including a plurality of sections (M1, M2, M3) extending in a 1st direction (D1); and a plurality of vias (V1, V2, V3) respectively protruding from the plurality of sections (M1, M2, M3) of the metal line (M). The plurality of sections (M1, M2, M3) have different thicknesses along the 1st direction (D1), and/or the vias (V1, V2, V3) have different widths (W1, W2, W3) in at least one of the 1st direction (D1) and a 2nd direction (D2) perpendicular to the 1st direction (D1), and have different protrusion heights in a 3rd direction (D3) perpendicular to the 1st and 2nd directions (D1, D2).