IC Interconnection Structure via Segmented Etch Stop Layers
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Solution Overview
Problem
Conventional interconnection structures in integrated circuits face issues due to misalignment errors during fabrication, leading to lateral etch regions, poor diffusion barrier adherence, voids in conductive vias, increased electromigration, and time-dependent dielectric breakdown, which affect the reliability and performance of the circuits.
Innovation Solution
The method involves forming conductive elements within dielectric layers, using multiple etch stop layers and selective deposition of conductive interfaces, and depositing diffusion barriers to prevent lateral etching and ensure proper filling of conductive vias, while also using specific materials like silicon nitride, titanium nitride, and cobalt tungsten boron to enhance adherence and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional single etch stop layer is used, then fabrication process is simple, but lateral etch regions occur causing misalignment errors
Solution Approach 1:
The single etch stop layer is segmented into multiple etch stop layers (first etch stop layer and second etch stop layer) with different etch selectivities. The first etch stop layer prevents lateral etching into the dielectric material, while the second etch stop layer controls the etching depth to reach the conductive line. This segmentation resolves the contradiction by improving alignment precision through better etch control while maintaining reasonable process complexity.
Solution Approach 2:
Different regions of the etch stop structure are given different properties: the first etch stop layer has high etch selectivity to prevent lateral etching in critical areas, while the second etch stop layer has different etch characteristics to enable precise depth control. This local differentiation of etch properties allows simultaneous achievement of precise alignment and controlled fabrication complexity.
2Quantity of substance
If thin diffusion barrier is deposited, then via filling is improved, but barrier adherence becomes poor leading to voids
Solution Approach 1:
A conductive interface layer is deposited preliminarily on the conductive line surface before depositing the diffusion barrier. This preliminary action creates a graded transition that improves barrier adherence and prevents void formation. The conductive interface layer acts as an intermediate layer that ensures both good adherence and proper via filling, resolving the contradiction between these two requirements.
3Area of moving object
If lateral etch region is small, then via size is reduced, but diffusion barrier coverage becomes insufficient
Solution Approach 1:
The diffusion barrier deposition is segmented into multiple stages: first depositing on the via walls, then performing a planarization step, and finally depositing additional barrier material to ensure complete coverage of the lateral etch region. This segmented approach ensures adequate barrier coverage even when the lateral etch region is small, while maintaining precise via dimensions.
4Measurement precision
If misalignment error occurs, then photolithographic tolerance is improved, but lateral etching increases causing critical distance violation
Solution Approach 1:
The first etch stop layer is positioned beforehand to extend beyond the conductive line edges, creating a protective cushion that prevents lateral etching from reaching the dielectric material and violating the critical distance between lines. This prior cushioning allows greater photolithographic alignment tolerance while preventing harmful lateral etch damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents lateral etch regions, ensures reliable contact between conductive lines and vias, reduces electromigration, and enhances the structural integrity of the interconnection structure, leading to improved performance and reliability of the integrated circuits.
Implementation Method 1
the dielectric material D2 is first etched (shown as arrows) using a first chemical reagent until the etch stop layer S1 is reached, then a second chemical reagent is used to etch the etch stop layer S1
Implementation Method 2
diffusion barriers B2, B2′, B2′′. The barriers B2, B2′, B2′′ are then generally covered with a 'seed layer' of a conductive material
Implementation Method 3
diffusion barriers B2, B2′, B2′′ are deposited on the sidewalls and bottoms of holes H2, H2′
Data Source
AI summary
The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.