Subtractively Patterned IC Interconnects With Selective Via Barriers
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Solution Overview
Problem
As integrated circuit (IC) density increases, interconnect parasitics such as resistance-capacitance (RC) delay become significant due to the density of interconnect structures, and the use of diffusion barrier materials in interconnects leads to higher electrical resistance, particularly at unnecessary locations, which can be detrimental to performance.
Innovation Solution
The implementation of subtractively patterned interconnect structures using multiple patterning operations and material compositions to reduce misregistration errors and incorporate bottom barrier materials selectively, reducing the impact of diffusion barriers on via resistance and leveraging techniques like area selective deposition and air gap fabrication to enhance interconnect performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion barrier material is used in all interconnect locations, then metal diffusion is prevented, but electrical resistance increases significantly
Solution Approach 1:
The patent applies diffusion barrier material selectively only at the via bottom where metal diffusion is most critical, rather than coating the entire via sidewall. This localized application maintains diffusion prevention where needed while minimizing resistance increase in current-carrying regions.
Solution Approach 2:
The invention extracts the diffusion barrier function from the general via structure and concentrates it only at the critical interface between the via and underlying interconnect, removing unnecessary barrier material from other locations where it contributes to resistance without providing proportional protection.
2Productivity
If via aspect ratio is increased to accommodate higher density, then device density improves, but via fabrication difficulty increases
Solution Approach 1:
The patent performs preliminary via opening formation and barrier material deposition before final via fill operations. This sequencing allows for better control of high aspect ratio via dimensions and facilitates subsequent metal fill processes by establishing proper barrier coverage and via geometry in advance.
Solution Approach 2:
The via fabrication process is segmented into distinct stages: via opening formation, barrier material deposition at specific locations, and selective removal of excess barrier material. This segmentation allows each step to be optimized independently for high aspect ratio vias.
3Reliability
If barrier material is deposited at via bottom, then diffusion is prevented, but via resistance increases
Solution Approach 1:
The patent deposits barrier material with spatial selectivity at the via bottom region only, creating a localized diffusion barrier that prevents metal migration at the critical interface while leaving the via sidewalls and top regions free of additional resistance-contributing materials.
Solution Approach 2:
The invention applies barrier material in a controlled, partial manner only where absolutely necessary for diffusion prevention, rather than applying excessive barrier coverage throughout the entire via structure. This minimizes the total amount of resistive material in the current path.
Data Source
AI summary
IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.