IC I/O Testing Segmentation via Analog Bus Wrappers
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Solution Overview
Problem
Current methods for testing integrated circuits (ICs) are costly and inefficient, particularly due to the high cost of test equipment and the inability to keep pace with IC performance requirements, especially for high-speed source synchronous systems, and existing standards like IEEE 1149.4 require excessive resources and dedicated pins for testing.
Innovation Solution
The implementation of a Self-Test and Repair I/O System (SIS) that segments I/O circuits into manageable segments, using analog and delay test wrappers, and soft wrappers to provide sequential access for testing without dedicated pins, allowing for efficient testing of hundreds or thousands of I/Os with a few tens of pins, reducing test time and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each I/O pin is tested using external test equipment, then testing completeness is improved, but test cost increases
Solution Approach 1:
The patent segments the I/O testing function into two parts: (1) external test equipment provides parametric measurement capability through a reduced set of pins, and (2) on-chip test circuits perform the actual testing of all I/O pins. This segmentation allows complete I/O testing without requiring external equipment for each pin, thereby reducing test cost while maintaining testing completeness.
Solution Approach 2:
The patent introduces on-chip test circuits as an intermediary between the external test equipment and the I/O pins. These on-chip circuits act as mediators that receive control signals from external equipment and automatically perform testing of all I/O pins, eliminating the need for external equipment to directly interface with each pin and thus reducing test cost.
2Reliability
If traditional external test equipment is used, then testing capability is improved, but test speed deteriorates
Solution Approach 1:
The patent implements self-service testing where the I/O circuits under test perform their own testing through on-chip test circuits. The tested circuits generate their own test signals and evaluate their own performance, eliminating the speed bottleneck of external test equipment and enabling test speeds that match or exceed IC performance requirements.
Solution Approach 2:
The patent merges the test signal generation, test execution, and result evaluation functions into integrated on-chip test circuits. This consolidation allows the testing system to operate at high speeds by eliminating the external equipment speed limitation and enabling the test system to keep pace with fast IC performance.
3Extent of automation
If IEEE 1149.4 standard is used for testing, then automated test capability is improved, but pin requirements increase
Solution Approach 1:
The patent makes existing I/O pins multi-functional by enabling them to serve both as normal operational pins and as test access points. The on-chip test circuits allow any I/O pin to be tested through the segmented analog bus interface, eliminating the need for dedicated test pins and achieving automated testing with reduced pin requirements.
Solution Approach 2:
The patent extracts the automated test capability from the physical I/O pins themselves and implements it within on-chip test circuits. This extraction allows the pins to be used for their primary function while the embedded circuits provide automated testing, thereby reducing pin requirements while maintaining automated test capability.
4Reliability
If comprehensive DFT/BIST approaches are used, then testing thoroughness is improved, but on-chip area increases
Solution Approach 1:
The patent segments the testing functionality into distributed on-chip test circuits that are integrated within each I/O subsystem rather than using a comprehensive centralized DFT/BIST approach. This segmentation provides thorough testing of each I/O segment while minimizing the area overhead by placing only essential test circuits locally rather than implementing extensive built-in self-test logic across the entire chip.
Data Source
AI summary
Integrated circuit test circuits may include at least an instruction processor and input-output subsystems. Input-output subsystems are segmented together into input-output subsystem segments. Each input-output subsystem includes an analog wrapper circuit (IW-A) operable to connect an input-output port to analog buses and further operable to isolate the input-output port from the buses, an integrated wrapper for delay test circuit (IW-D) operable to control a delay test sequence, and a soft wrapper circuit operable to control the IW-A and the IW-D, the soft wrapper circuit being directed by the instruction processor.