Integrated Circuit IO Signal Timing Difference Detection
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Solution Overview
Problem
The testing of integrated circuits, particularly the measurement of alternate current (AC) characteristics of input/output (IO) signals, is complex and time-consuming, requiring months or years to design accurate tests and involves intricate setup and hold/skew time measurements that are challenging to synchronize.
Innovation Solution
A tester and method that translate IO tests into timing differences between signals, using a signal generator to provide signals to paths within the integrated circuit, with a processor detecting time differences by comparing test results and altering the predefined period to achieve high accuracy, allowing for testing under various ambient conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional AC characterization testing methods are used for IO signals, then measurement precision is improved, but device complexity and testing time increase significantly
Solution Approach 1:
The patent extracts the timing difference measurement function from the complex AC characterization testing. By isolating the core measurement task to detecting time differences between signal transitions, the solution simplifies the tester architecture while maintaining measurement accuracy for IO signal characteristics.
Solution Approach 2:
The patent replaces complex electrical AC characterization measurements with a timing-based detection mechanism. Instead of directly measuring AC parameters which requires complex synchronization and signal generation, the system uses simple timing difference detection between signal edges to infer the same information, significantly reducing tester complexity.
2Measurement precision
If traditional AC characterization testing methods are used for IO signals, then measurement precision is improved, but testing duration increases
Solution Approach 1:
The patent extracts the essential measurement function to timing difference detection, eliminating unnecessary complex AC characterization procedures. This extraction reduces testing duration by focusing only on the critical timing parameters that define IO signal behavior, while still achieving the required measurement precision.
Solution Approach 2:
The patent skips the lengthy traditional AC characterization testing process by directly measuring timing differences between signal transitions. This approach rushes through the testing process by eliminating redundant measurements and focusing only on the essential timing parameters, significantly reducing test duration without sacrificing accuracy.
3Measurement precision
If setup/hold/skew time measurements are performed with strict synchronization solutions, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the timing measurement function from the complex synchronization system. By directly measuring time differences between signal transitions without requiring complex synchronization mechanisms, the solution achieves precise timing measurements while significantly reducing the complexity of the synchronization infrastructure.
Solution Approach 2:
The patent replaces complex synchronization hardware and control mechanisms with a simpler timing difference detection approach. Instead of using strict synchronization solutions that require coordinated clock signals and complex control logic, the system uses straightforward timing measurement between signal edges to achieve the same measurement precision with much lower complexity.
Data Source
AI summary
A method for testing an integrated circuit, that includes: (a) providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad, and providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad; (b) comparing between a first test result and a second test result, wherein the first test result represents a state of the first memory element sampled a predefined period after a provision of the first signal and the second test result represents a state of the second memory element sampled a predefined period after a provision of the second signal; (c) altering the predefined period; and (d) repeating the stages of providing, comparing and altering until detecting a time difference between a first path propagation period and a second path propagation period.