Integrated Circuit Isolation Layout for ESD Parasitic NPN Suppression
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Solution Overview
Problem
In integrated circuits, parasitic NPN transistors can form when two N wells are biased by different pads, leading to potential failure during ESD events due to filament formation.
Innovation Solution
The integrated circuit incorporates conductivity reduction features, including P+ isolation regions and conductive tie biasing structures that are not electrically connected, to increase the resistivity of current paths to the base electrode of parasitic NPN transistors, thereby reducing current flow during ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two N wells are placed in close proximity and biased by different pads, then device integration density is improved, but parasitic NPN transistors can activate during ESD events causing substrate damage
Solution Approach 1:
A P-type isolation region is introduced as an intermediary structure between two closely-spaced N wells. This P-type region acts as a mediator that prevents direct interaction between the N wells, thereby blocking the formation and activation of parasitic NPN transistors during ESD events while allowing the N wells to remain in close proximity for high integration density.
Solution Approach 2:
The patent applies localized P-type doping in specific regions between N wells to create isolation zones. By modifying the local electrical properties (introducing P-type carriers) in targeted areas, the patent prevents parasitic transistor activation only where needed, without affecting the overall device performance or requiring complete redesign of the N well structure.
2Reliability
If conductivity reduction features are added between N wells, then parasitic NPN transistor activation is reduced, but device complexity increases
Solution Approach 1:
The patent changes the electrical parameters (carrier type and concentration) in specific regions by introducing P-type doping. This parameter change creates a conductivity barrier that inhibits parasitic transistor activation. The solution modifies the physical state (electrical properties) of the isolation region rather than adding complex structural elements, thereby achieving reliability improvement with minimal complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The conductivity reduction features effectively inhibit the activation of parasitic NPN transistors during ESD events, reducing the risk of substrate damage and allowing for closer device placement without incurring damage, especially for higher voltage applications.
Implementation Method 1
conductivity reduction features that increase the resistivity of current paths to a P type region of one device
Implementation Method 2
conductive tie biasing structures where the conductive tie biasing structures are not electrically connected to each other or electrically coupled to each other by another conductive biasing structure. One of the conductive tie biasing structures is located between the two devices
Data Source
AI summary
An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.