Integrated Circuit Isolation Error Checking via Reference Value Comparison
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Solution Overview
Problem
Existing methods for testing isolation values of isolation cells in integrated circuits are time-consuming and resource-intensive, requiring significant computational resources and often relying on operator experience.
Innovation Solution
An operating method for an electronic device that simulates an integrated circuit design, using a processor to obtain power domain structures, current and reference isolation values, and reset values to quickly check isolation errors by comparing these values and correcting them as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods are used to test isolation values of isolation cells, then comprehensive testing can be performed, but it requires a long time and a lot of computation resources
Solution Approach 1:
The patent applies preliminary action by determining reference isolation values during the design phase before actual operation. These reference values are stored and later used for quick comparison during runtime, eliminating the need for time-consuming traditional testing while maintaining comprehensive validation coverage
Solution Approach 2:
The patent creates a simplified model by copying only the essential isolation value data into a lookup table structure. This copied representation allows for rapid comparison operations without requiring access to the full complex testing infrastructure, significantly reducing computation resources and time
2Reliability
If traditional testing methods are used to test isolation values of isolation cells, then comprehensive testing can be performed, but it requires a lot of computation resources such as memory and processing resources
Solution Approach 1:
The patent creates a simplified model by copying only the essential isolation value data into a lookup table structure. This copied representation allows for rapid comparison operations without requiring access to the full complex testing infrastructure, significantly reducing computation resources and time
Solution Approach 2:
The patent changes the parameter of data representation from full test cases to compact reference value tuples. By transforming the isolation value data into a more efficient parameter format (current isolation value, reference isolation value, reset value), the system achieves the same validation goal with minimal memory and processing requirements
3Reliability
If isolation values are incorrectly specified, then the circuit may abnormally operate, but detecting these errors through traditional methods is time-consuming
Solution Approach 1:
The patent implements feedback by continuously comparing current isolation values against stored reference values during operation. When a mismatch is detected, the system immediately identifies the error and can trigger corrective actions, providing real-time validation that maintains circuit reliability while enabling rapid error detection
Solution Approach 2:
The patent applies preliminary action by determining reference isolation values during the design phase before actual operation. These reference values are stored and later used for quick comparison during runtime, eliminating the need for time-consuming traditional testing while maintaining comprehensive validation coverage
Data Source
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AI summary
Disclosed is an operating method of an electronic device which simulates a design of an integrated circuit. The method includes detecting, at the electronic device, a power domain structure of the integrated circuit from a register transfer level (RTL) model of the integrated circuit, detecting, at the electronic device, current isolation values of ports of the integrated circuit from the power domain structure of the integrated circuit and an unified power format (UPF) of the integrated circuit, detecting, at the electronic device, reference isolation values of the ports of the integrated circuit, detecting, at the electronic device, reset values of the ports of the integrated circuit, and checking, at the electronic device, isolation errors of the ports of the integrated circuit based on the current isolation values, the reference isolation values, and the reset values.