IC Isolator Structure Using Series Diodes to Cut Parasitic Capacitance
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Solution Overview
Problem
Conventional isolator structures in integrated circuits suffer from significant parasitic capacitance, which attenuates signal levels and is difficult to reduce without compromising high voltage isolation capabilities or increasing manufacturing costs.
Innovation Solution
The implementation of an isolator structure with patterned metal conductor elements separated by dielectric material, where the lower element overlies a substrate of one conductivity type surrounded by doped regions of a second conductivity type, and reverse biasing the p-n junctions to reduce parasitic capacitance without affecting high voltage isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolator structures with multiple interlevel dielectric layers are used, then high voltage isolation capability is achieved, but parasitic capacitance increases significantly
Solution Approach 1:
The patent extracts and removes the problematic parasitic capacitance source by eliminating the lower plate from the capacitor structure. This leaves only the upper plate floating above the substrate, separated by a single interlevel dielectric layer, thereby removing the parasitic capacitance path between the lower plate and substrate while maintaining the high voltage isolation function through the remaining dielectric structure.
Solution Approach 2:
The patent converts the harmful effect of parasitic capacitance into a beneficial design feature by intentionally creating a structure where the capacitor plate is positioned to exploit the natural dielectric properties of the interlevel layer. The floating upper plate configuration transforms what would normally be a parasitic effect into a controlled capacitive structure with minimized unwanted capacitance, improving signal integrity while maintaining voltage isolation.
2Object-generated harmful factors
If the cumulative thickness of interlevel dielectric layers is increased to reduce parasitic capacitance, then manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the need for multiple thick dielectric layers by extracting the lower plate structure. This simplification allows the use of a single standard-thickness interlevel dielectric layer to achieve the same parasitic capacitance reduction that would otherwise require stacking multiple dielectric layers, thereby reducing manufacturing complexity while maintaining electrical performance.
3Reliability
If lower plate is formed in lower metal level, then high voltage isolation is maintained, but parasitic capacitance between lower plate and substrate increases
Solution Approach 1:
The patent removes the lower plate entirely from the structure, eliminating the source of parasitic capacitance between the lower plate and substrate. The high voltage isolation function is maintained by the floating upper plate and its separation from the substrate through the interlevel dielectric layer, achieving both goals simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by up to 40% while maintaining high voltage isolation performance, and can be fabricated using existing manufacturing processes without adding metal levels, thereby improving signal integrity and reducing manufacturing costs.
Implementation Method 1
reverse biasing the p-n junctions to reduce parasitic capacitance without affecting high voltage isolation
Data Source
AI summary
Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.