Integrated Circuit Jitter Reduction via Partitioned Design Blocks
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Solution Overview
Problem
Integrated circuits (ICs) face increasing jitter issues due to higher input clock frequencies and increased functionality, which degrades performance and can lead to system failure, necessitating effective methods to manage and reduce output jitter during the design phase.
Innovation Solution
The approach involves partitioning circuit designs into blocks, coupling them with a core clock and mutually exclusive enable signals, and using a clock manager circuit to generate clock outputs with different phases, thereby distributing jitter across multiple clock cycles and reducing switching noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency and functionality are increased to improve throughput, then productivity is improved, but jitter increases degrading performance
Solution Approach 1:
The circuit design is divided into multiple partitioned design blocks, each handling a subset of the total functionality. This segmentation distributes the switching noise across multiple smaller blocks rather than having all blocks switch simultaneously, thereby reducing jitter while maintaining high throughput and functionality.
2Productivity
If all design blocks are enabled simultaneously to maximize functionality, then productivity is improved, but switching noise and jitter increase
Solution Approach 1:
Mutually exclusive enable signals are used to activate different partitioned design blocks in a periodic manner across clock cycles. This ensures that not all blocks are enabled simultaneously, reducing switching noise while still providing full functionality over time through the periodic activation of different partitions.
3Reliability
If partitioned design blocks are used to reduce jitter, then jitter performance is improved, but device complexity increases
Solution Approach 1:
A clock manager circuit is introduced as an intermediary component that generates the mutually exclusive enable signals for the partitioned design blocks. This centralized control mechanism simplifies the overall design by providing a systematic way to manage the enabling of partitions, reducing the complexity that would otherwise arise from coordinating multiple partitions manually.
Data Source
AI summary
Methods and circuits to reduce jitter in a design block including partitioning the design block. A circuit design is partitioned into multiple partitioned design blocks performing the same task as the original circuit deign. In one embodiment, a core clock signal is supplied to each of the partitioned design blocks, having a frequency higher than frequency of the reference clock signal. Additionally each of the partitioned design blocks receives a mutually exclusive enable signal, where each of the partitioned design blocks may be activated once at a given time.