IC Lateral Power Routing for Signal Interference Isolation

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Solution Overview

Problem

Traditional integrated circuit (IC) design faces issues with signal interference due to power influence, leading to lower success rates and unnecessary coupling effects, particularly in high I/O chip requirements, as power and signal paths are often placed on the same side of the IC.

Innovation Solution

The electronic device incorporates a power supply element with lateral electrical interconnections, allowing power to be received laterally and signals to be transmitted non-laterally, using a power delivery network exposed on the lateral surface of the integrated circuit layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If power and signal paths are placed on the same side of the IC, then the device structure is simplified, but signal interference increases and IC performance deteriorates

Engineering Contradiction:
Improvedevice structureVSAvoidIC performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent transitions from traditional planar power and signal routing to a three-dimensional vertical architecture. Power delivery networks are implemented through multiple stacked layers with vertical interconnects, separating power paths from signal paths in the vertical dimension while maintaining compact lateral footprint. This dimensional transition eliminates signal interference while preserving device integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If power delivery network is fully enclosed within the IC layer, then the IC performance is optimized, but the lateral side exposure for power reception is reduced

Engineering Contradiction:
ImproveIC performanceVSAvoidlateral side exposure
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements a nested hierarchical structure where the power delivery network is contained within encapsulant layers that form protective shells. Multiple PDN layers are nested within the encapsulant matrix, with each layer providing power distribution while being protected and organized by the encapsulant structure. This nesting allows full enclosure for performance optimization while maintaining lateral access points through the encapsulant.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Length of stationary object

If the electronic device thickness is reduced, then the device integration is improved, but the power delivery path length is reduced affecting power reception

Engineering Contradiction:
Improvedevice thicknessVSAvoidpower reception
Core Design Contradiction:
Length of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent implements non-uniform power delivery path design where the encapsulant thickness and PDN layer positioning are locally optimized. Regions with higher power demand have shorter vertical power paths through strategically positioned PDN layers, while other regions can have greater thickness for encapsulation and protection. This local quality variation maintains short power paths for efficient power reception while achieving overall device thinness.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250309073A1Electronic device
Publication Date: 2025.10.02 ADVANCED SEMICON ENG INC
  • US20250309073A1 patent drawing
  • US20250309073A1 patent drawing
  • US20250309073A1 patent drawing

AI summary

The present disclosure provides an electronic device. The electronic device includes an electronic component configured to laterally receive a power and configured to non-laterally transmit a signal. The electronic component includes an integrated circuit layer configured to receive the power.