IC Layer Overlap Prediction for Contact Resistance Optimization
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Solution Overview
Problem
The scaling of contacts and interconnects in integrated circuits (ICs) leads to increased resistance and misalignment issues, affecting RC delay, operating frequency, and reliability, which current design rules struggle to address effectively, especially in advanced process nodes like 10/7 nm.
Innovation Solution
A method using machine-trained neural networks to predict and display minimum overlap shapes for semiconductor layer interfaces, accounting for process variations and misalignments, allowing designers to optimize layouts for reduced resistance and improved reliability through interactive design updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If contact and interconnect dimensions are scaled down to maintain transistor scaling, then device density and integration are improved, but resistance increases significantly
Solution Approach 1:
The patent applies preliminary action by predicting the manufactured contours and minimum overlap shapes before actual fabrication occurs. The system uses machine-trained neural networks to anticipate process variations and misalignments, allowing designers to optimize contact layouts in advance to ensure adequate overlap and minimize resistance even when dimensions are scaled down.
2Manufacturing precision
If overlay accuracy is increased to maintain alignment precision, then manufacturing complexity and process control requirements increase
Solution Approach 1:
The patent applies partial action by focusing computational resources on predicting only the critical minimum overlap shapes and contours that directly impact contact resistance, rather than attempting to model and control all aspects of the manufacturing process. This selective approach provides sufficient precision for optimization without requiring complete process control.
3Reliability
If design rules are made more stringent to account for process variations, then manufacturing robustness is improved, but design flexibility and productivity decrease
Solution Approach 1:
The patent applies self-service by enabling designers to independently predict and optimize their own contact overlap shapes using the machine-trained neural network tool. Instead of relying on conservative foundry-imposed design rules that reduce productivity, the system allows designers to self-verify and self-optimize their layouts against predicted manufacturing variations, maintaining both robustness and flexibility.
Data Source
AI summary
Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.