IC Layout Adjustment for Dielectric Reliability at Interconnects
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Solution Overview
Problem
As integrated circuit feature sizes shrink below 45 nm, sub-wavelength lithography challenges arise, leading to narrow process windows and increased risk of via misalignment, which accelerates time-dependent dielectric breakdown due to higher electric fields across dielectric materials, limiting wiring density and maximum supply voltage.
Innovation Solution
A layout adjustment method that selectively increases via-to-wire spacing by shifting and thinning wire segments, and rotating vias, while maintaining design rule compliance, to reduce dielectric stress and enhance time-dependent dielectric breakdown reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If via-to-wire spacing is reduced to increase wiring density, then productivity is improved, but dielectric reliability deteriorates due to higher electric fields accelerating time-dependent dielectric breakdown
Solution Approach 1:
The patent applies local quality by selectively adjusting via-to-wire spacing only in critical regions where dielectric breakdown risk is highest, rather than uniformly increasing spacing across the entire layout. The method identifies interconnects susceptible to dielectric breakdown and applies layout adjustments specifically to those areas, maintaining high wiring density in low-risk regions while improving reliability in critical areas.
Solution Approach 2:
The patent changes the geometric parameters of the layout by shifting wire segments and rotating vias to increase via-to-wire spacing in specific locations. This parameter adjustment modifies the electric field distribution and reduces dielectric stress in critical areas, thereby improving time-dependent dielectric breakdown reliability without compromising overall wiring density.
2Reliability
If via-to-wire spacing is increased to improve dielectric reliability, then dielectric mean time to failure is improved, but wiring density is reduced
Solution Approach 1:
The method implements local quality by applying via-to-wire spacing adjustments only in specific critical regions where dielectric breakdown is most likely to occur, rather than uniformly across the entire layout. This selective approach maintains high wiring density in low-risk areas while improving reliability in critical areas.
Solution Approach 2:
The patent performs preliminary analysis to identify interconnects that are most susceptible to dielectric breakdown based on their geometric configuration and electrical characteristics. This preliminary identification allows the layout adjustment to be applied proactively to the most critical areas before dielectric breakdown occurs, optimizing the balance between reliability and wiring density.
3Productivity
If sub-wavelength lithography is used to reduce feature sizes below 45 nm, then productivity is improved, but manufacturing precision deteriorates due to increased via misalignment risk
Solution Approach 1:
The patent applies preliminary action by performing layout adjustments before manufacturing to compensate for expected via misalignment. The method proactively modifies the layout by shifting wires and rotating vias to create alignment tolerance, ensuring that even with sub-wavelength lithography limitations, the final via-to-wire spacing maintains adequate dielectric reliability.
Solution Approach 2:
The patent implements preliminary anti-action by designing the layout in advance to counteract the harmful effect of via misalignment. By pre-adjusting wire positions and via orientations, the method creates a layout that is inherently more tolerant to misalignment, effectively neutralizing the negative impact of sub-wavelength lithography limitations before manufacturing occurs.
Data Source
AI summary
Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.