Integrated Circuit Layout Generation Using Body Biased Rows
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Solution Overview
Problem
Current techniques for designing integrated circuit blocks using standard cells struggle to optimize switching speed and leakage power simultaneously through body biasing, as existing methods either increase leakage power when improving switching speed or vice versa.
Innovation Solution
A method is introduced that involves identifying and constraining specific standard cells to be placed in body biased rows within the integrated circuit layout, where only one type of transistor is body biased, allowing for improved switching speed or reduced leakage current without significant impact on the other parameter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If forward body biasing is applied to transistors to increase switching speed, then switching speed is improved, but leakage power increases
Solution Approach 1:
The standard cell library is segmented into multiple types of standard cells, each optimized for different body biasing strategies. Some standard cells are designed with transistors configured to benefit from forward body biasing (FBB) while others are designed for reverse body biasing (RBB), allowing the placement tool to selectively assign cells to appropriate rows based on the desired performance characteristics.
Solution Approach 2:
Different rows in the circuit layout are assigned different body biasing characteristics. FBB rows are created to enhance switching speed in critical paths, while RBB rows are used to reduce leakage power in non-critical areas. The placement tool constrains specific standard cells to specific row types, creating local optimization throughout the circuit.
2Loss of energy
If reverse body biasing is applied to transistors to reduce leakage current, then leakage power is reduced, but switching speed decreases
Solution Approach 1:
The standard cell library is segmented into multiple types of standard cells, each optimized for different body biasing strategies. Some standard cells are designed with transistors configured to benefit from forward body biasing (FBB) while others are designed for reverse body biasing (RBB), allowing the placement tool to selectively assign cells to appropriate rows based on the desired performance characteristics.
Solution Approach 2:
Different rows in the circuit layout are assigned different body biasing characteristics. FBB rows are created to enhance switching speed in critical paths, while RBB rows are used to reduce leakage power in non-critical areas. The placement tool constrains specific standard cells to specific row types, creating local optimization throughout the circuit.
3Ease of manufacture
If standard cells are freely placed to fulfill functional design requirements, then routing overhead is reduced, but body biasing optimization is lost
Solution Approach 1:
The standard cell library is segmented into multiple types of standard cells, each optimized for different body biasing strategies. Some standard cells are designed with transistors configured to benefit from forward body biasing (FBB) while others are designed for reverse body biasing (RBB), allowing the placement tool to selectively assign cells to appropriate rows based on the desired performance characteristics.
Solution Approach 2:
The standard cell library is pre-configured with multiple cell types optimized for different body biasing strategies before the placement process. This preliminary classification allows the automated placement tool to efficiently constrain cells to appropriate rows without significantly increasing placement complexity or routing overhead.
Data Source
AI summary
A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row. Constraint data is specified identifying a subset of the standard cells that are allowed to be placed in each body biased row, and the layout is then generated by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row, and the constraint data for each body biased row. This enables a significant improvement in the benefits that can be achieved through the use of body biasing mechanisms, for example allowing a significant increase in switching speed of the circuit block to be achieved, without a significant increase in leakage current.