IC Layout Boundary Scaling via Feature Merging
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Solution Overview
Problem
In integrated circuit (IC) layout design, the requirement to maintain a minimum distance between layout features restricts scaling, leading to reduced active areas and increased resistivity, which degrades IC performance.
Innovation Solution
An automated layout tool modifies the IC layout by merging or removing portions of standard cells to increase the distance between features to meet design rule requirements, allowing for scalable design without manual intervention and maintaining electrical integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the minimum distance between layout features is maintained according to design rules, then manufacturing reliability is improved, but the active area scales down and resistivity increases
Solution Approach 1:
The patent divides the layout verification process into two levels: standard cell level and IC level. At the standard cell level, design rules are strictly enforced to ensure manufacturing reliability. At the IC level, the system segments the analysis to identify boundary regions where features from adjacent standard cells are close but not violating rules, allowing selective relaxation of distance constraints in these specific regions while maintaining overall reliability.
Solution Approach 2:
The patent applies different distance constraints to different regions of the layout. In boundary regions between standard cells, where features from adjacent cells are close, the system allows reduced spacing. In non-boundary regions, full design rule constraints are maintained. This local differentiation enables area optimization in critical boundary zones without compromising manufacturing reliability in other regions.
2Reliability
If the minimum distance between layout features is maintained according to design rules, then manufacturing reliability is improved, but IC performance degrades due to increased resistivity
Solution Approach 1:
The patent segments the layout into boundary regions and non-boundary regions, applying differentiated distance constraints. In boundary regions between standard cells, the system identifies features that are close due to cell adjacency and allows reduced spacing, thereby reducing resistivity and improving power performance without affecting manufacturing reliability in critical non-boundary regions.
Solution Approach 2:
The patent implements local quality by applying relaxed distance constraints specifically in boundary regions where standard cells abut, while maintaining strict constraints elsewhere. This enables reduced resistivity and improved power performance in boundary regions without compromising manufacturing reliability in regions where full design rules apply.
3Extent of automation
If automated layout modification is implemented to merge or remove portions of standard cells, then layout scalability is improved and manual intervention is reduced, but complexity of layout modification increases
Solution Approach 1:
The patent performs preliminary actions by pre-identifying boundary regions between standard cells and pre-determining which layout features are close due to cell adjacency. This preliminary analysis enables the automated system to make informed decisions about which features to modify, reducing the complexity of the modification process itself while maintaining high automation extent.
Solution Approach 2:
The patent implements self-service by enabling the automated layout modification tool to independently identify boundary regions, select features for modification, and apply appropriate changes without manual intervention. The system serves itself by using its own analysis capabilities to guide the modification process, reducing both manual overhead and overall system complexity.
Data Source
AI summary
Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.