Hierarchical IC Layout Data Correction for CD Variation
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Solution Overview
Problem
Current data correction techniques for integrated circuit layouts require high computational costs and time due to the need for flattening hierarchies to address long range critical dimension variations, which leads to inefficient processing and loss of hierarchical advantages.
Innovation Solution
A method that involves receiving a CD compensation map, grouping compensation amounts into multiple ranges, generating target layers, superimposing compensation regions over these layers, performing data correction on both the layout and target shapes separately, and combining the results based on the CD compensation map to efficiently accommodate long range critical dimension variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data correction is performed on flattened hierarchical layouts to address long range CD variations, then manufacturing precision is improved, but computational cost and processing time increase significantly
Solution Approach 1:
The patent segments the hierarchical layout into multiple levels (e.g., module level and cell level) and applies different correction strategies to each level. Long range CD variations are corrected at the module level using coarse corrections, while optical proximity corrections are applied at the cell level, thereby reducing overall computational cost while maintaining precision.
Solution Approach 2:
The patent applies different correction qualities to different regions of the layout. Critical areas requiring high precision receive detailed OPC corrections, while less critical regions receive simplified corrections. This local differentiation maintains manufacturing precision where needed without unnecessarily increasing computational cost across the entire layout.
2Manufacturing precision
If hierarchy is flattened to enable differentiated corrections for leaf cells in different contexts, then manufacturing precision is improved, but processing time and computational resources increase
Solution Approach 1:
The patent maintains the hierarchical structure by segmenting the layout into parent modules and child cells, allowing corrections to be applied at different levels simultaneously. This avoids the need to flatten the entire hierarchy while still enabling differentiated corrections for leaf cells in different contexts through context-aware correction algorithms.
Solution Approach 2:
The patent performs preliminary corrections at higher hierarchy levels (module level) before applying detailed corrections at lower levels (cell level). This preliminary action handles the bulk of the correction work early, reducing the computational burden on subsequent detailed corrections and overall processing time.
3Manufacturing precision
If optical radius is increased to account for more adjacent shapes in OPC calculations, then manufacturing precision is improved, but the likelihood of requiring hierarchy flattening increases
Solution Approach 1:
The patent applies different optical radii to different hierarchy levels. At the module level, a larger optical radius is used to capture long range CD variations, while at the cell level, a smaller optical radius suffices for detailed OPC. This local differentiation maintains precision without requiring hierarchy flattening throughout the entire layout.
Solution Approach 2:
By segmenting the correction process into multiple hierarchy levels, the patent can independently optimize the optical radius for each level. This allows accurate long range CD variation compensation at the module level without propagating the need for hierarchy flattening down to the cell level.
Data Source
AI summary
A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.