IC Layout Hash Matching for CMP Hotspot Prediction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing process for identifying and addressing topology hotspots in integrated circuit manufacturing, such as those caused by Chemical Mechanical Polish (CMP), is time-consuming and inefficient, requiring multiple phases and taking up to three months to detect and correct defects after the manufacturing process is completed.
Innovation Solution
A method that predicts hotspots in the integrated circuit manufacturing process using a hotspot prevention model, which involves generating hash values from cropped images of wafer layouts, grouping similar hash values, constructing a hotspot library, and selecting an optimal CMP recipe to minimize hotspot occurrence before physical wafer processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical wafer processing and measurement are performed to identify hotspots, then manufacturing precision is ensured, but time consumption increases significantly
Solution Approach 1:
The patent extracts layout images and generates hash values before physical wafer processing to identify potential hotspots in advance. By performing the defect prediction analysis on layout data prior to manufacturing, the system can flag problematic regions before they become actual defects on physical wafers, thereby maintaining detection accuracy while dramatically reducing the time required for defect identification.
Solution Approach 2:
The patent creates a digital copy of the wafer layout by extracting layout images and converting them into hash values for comparison. Instead of directly measuring physical wafers to identify hotspots, the system uses a virtual model (hash representation) to predict defect locations, which then guides physical inspection. This copying approach maintains precision while reducing measurement time.
2Reliability
If multiple phases including design, layout, manufacturing, and measurement are performed sequentially, then comprehensive defect detection is achieved, but production cycle time increases
Solution Approach 1:
The patent performs hotspot prediction by extracting layout images and generating hash values during the design/layout phase, before manufacturing begins. This preliminary analysis identifies potential hotspots in advance, allowing manufacturers to focus physical measurement efforts only on predicted defect regions, thereby maintaining comprehensive detection while accelerating the overall production cycle.
Solution Approach 2:
The patent introduces hash values as an intermediary representation between the layout design and physical manufacturing. By comparing hash values of layout images against a database of known defective patterns, the system can predict hotspots without completing all traditional manufacturing and measurement phases sequentially, thus bridging the gap between design and production while improving throughput.
3Measurement precision
If layout images are extracted and hash values are generated for all regions, then hotspot prediction accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent divides the wafer layout into multiple discrete images and processes each separately to generate individual hash values. This segmentation allows the system to manage computational complexity by handling smaller, manageable units rather than processing the entire layout as one large image, while still achieving comprehensive hotspot prediction across the full wafer surface.
Solution Approach 2:
The patent transforms layout images into hash values, changing the parameter representation from pixel-based images to compact hash codes. This parameter transformation reduces the data complexity while preserving the essential features needed for hotspot prediction, enabling accurate comparison against the database without requiring excessive computational resources.
Data Source
AI summary
A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.