IC Layout Area Compaction via Interlocking Packing Keys
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Solution Overview
Problem
As semiconductor devices decrease in size, process performance variability increases, leading to a desire for more regular design layouts to reduce sensitivity, but existing methods result in larger device sizes, increased area costs, and reduced yield due to increased affected area by random defects.
Innovation Solution
The method involves determining physical extent boundaries for each layer of circuit blocks, establishing packing keys to define interlocking characteristics, and combining blocks based on packing compatibility to form clusters with reduced area, using a library of blocks and software tools for optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design layouts are made more regular to decrease sensitivity to process variability, then manufacturing precision is improved, but device area increases
Solution Approach 1:
The method segments the layout design process into multiple layers (e.g., active regions, gates, contacts, interconnects) and optimizes each layer independently while maintaining their spatial relationships. This allows regularity to be introduced at specific critical layers without forcing uniformity across the entire device, thereby reducing area while maintaining manufacturing precision.
Solution Approach 2:
The patent applies different levels of regularity to different regions and layers of the device based on their specific manufacturing requirements. Critical layers that require high precision for process variability control are made more regular, while non-critical areas maintain flexibility to minimize overall device area.
2Manufacturing precision
If semiconductor device size is increased to reduce sensitivity to process variability, then manufacturing precision is improved, but area costs increase
Solution Approach 1:
The method introduces dimensional differentiation by treating various layout layers as separate dimensions that can be independently optimized. By controlling regularity at specific layer dimensions rather than enforcing uniformity across all dimensions, the approach achieves process variability control without proportionally increasing the overall device footprint.
3Manufacturing precision
If device area is increased to reduce sensitivity to process variability, then manufacturing precision is improved, but yield decreases due to greater area affected by random defects
Solution Approach 1:
By segmenting the device into functionally independent modules or blocks with regular layouts, the method limits the propagation of random defects. If a defect occurs in one segment, it affects only that local region rather than the entire larger device area, thereby maintaining yield while achieving the necessary manufacturing precision through localized regularity.
4Productivity
If more blocks are packed per wafer to decrease area costs, then productivity is improved, but manufacturing precision decreases due to increased density
Solution Approach 1:
The method segments the wafer into multiple independent device units, each with internally regular layouts. This segmentation allows high-density packing of units on the wafer (improving productivity) while each unit maintains its own regularity characteristics (preserving manufacturing precision). The independence of segments prevents variability accumulation across the entire wafer.
Data Source
AI summary
A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.