IC Layout Contour Prediction for Interactive Manufacturability Editing
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Solution Overview
Problem
The increasing complexity of design rules in electronics engineering, particularly at smaller geometry process nodes, leads to design rule bloat and computational challenges in ensuring manufacturability, with traditional methods being too slow for interactive design and hotspot fixing due to the high computational expense of lithography simulations and OPC/ILT processes.
Innovation Solution
The use of machine-trained neural networks to predict manufactured wafer contours, allowing for fast edit loops and interactive design decisions, and leveraging concurrency with GPU acceleration to perform tasks related to manufacturing rule compliance, OPC/ILT effects, and lithography simulations, thereby simplifying design rules and improving manufacturability without compromising layout flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography simulation and OPC/ILT processes are used to ensure manufacturing compliance, then manufacturing precision is improved, but computational time and complexity increase significantly
Solution Approach 1:
The patent pre-computes and stores manufacturing contours for various design rule violations in a lookup table during an offline training phase. During interactive design, the system simply queries this pre-computed data rather than performing full lithography simulations, achieving fast feedback while maintaining accuracy.
Solution Approach 2:
The patent creates simplified contour models that replicate the essential manufacturing outcomes without requiring full lithography simulation. These contour models are trained to match reference simulations and can be quickly queried to predict manufacturing compliance, replacing expensive simulations with lightweight lookups.
2Manufacturing precision
If comprehensive design rule checking is performed to ensure manufacturability, then manufacturing precision is improved, but device complexity and computational expense increase
Solution Approach 1:
The patent divides the complex manufacturing compliance check into discrete contour models for different violation types (e.g., bridging, pinching, width violations). Each contour model handles a specific aspect of manufacturing compliance, allowing the system to query only relevant contours for each design feature rather than performing exhaustive full-chip simulations.
Solution Approach 2:
The patent uses lightweight contour lookup tables that can be quickly generated and discarded, replacing expensive, long-running lithography simulation processes. These simple contour data structures provide sufficient accuracy for interactive design without the computational burden of full simulations.
3Productivity
If interactive design feedback is provided rapidly, then productivity is improved, but measurement precision and simulation accuracy may be compromised
Solution Approach 1:
The patent replaces the mechanical lithography simulation process with a machine learning-based contour prediction system. The neural network model has been trained to accurately predict manufacturing contours from layout inputs, providing both speed and accuracy without requiring actual physical or computational lithography simulations during interactive design.
Data Source
AI summary
A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.