Integrated Circuit Layout Correction via Silicon Probing
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Solution Overview
Problem
Conventional methods for identifying and correcting defects in integrated circuit design layouts lack systematic and hierarchical analysis, leading to unsatisfactory product yield and difficulty in considering process and circuit layout interactions, especially when machine or processing conditions change.
Innovation Solution
A layout correcting method and system that involves analyzing performance parameters, selecting devices under test, performing computer simulations, and conducting direct on-chip probing using Boolean algebra to compare and correct the integrated circuit design layout based on differences between simulated and actual results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional methods (simple rules or physical models) are used to identify hotspots, then the analysis process is simple and fast, but the estimated hotspots are far from the real electrical performance and product yield is unsatisfied
Solution Approach 1:
The patent segments the analysis into multiple hierarchical stages: (1) initial hotspot identification using simple rules, (2) detailed electrical simulation of identified hotspots, (3) silicon verification through direct probing, and (4) iterative refinement. This segmentation allows the system to achieve high accuracy by focusing complex analysis only on critical areas rather than the entire layout.
Solution Approach 2:
The patent performs preliminary identification of potential hotspots using simple rules and physical models before conducting detailed electrical simulations. This preliminary action filters out non-critical areas, allowing subsequent complex analysis to be focused only on regions likely to contain actual performance issues, thereby improving both accuracy and efficiency.
2Reliability
If systematic and hierarchical analysis is performed to improve hotspot identification accuracy, then the estimated hotspots closely match real electrical performance, but the analysis process becomes more complex and time-consuming
Solution Approach 1:
The analysis process is divided into distinct hierarchical stages that can be executed sequentially: initial screening using simple rules, followed by detailed electrical simulation of identified hotspots, then silicon verification. This segmentation enables the system to achieve high reliability through comprehensive analysis while managing time loss by focusing intensive analysis only on critical regions identified in earlier stages.
Solution Approach 2:
Preliminary identification of hotspots using simple rules and physical models is performed before detailed electrical simulation. This preliminary action reduces the scope of subsequent complex analysis to only the most critical regions, thereby maintaining high product yield through systematic analysis while minimizing overall analysis time.
3Adaptability or versatility
If conventional methods are used without considering surrounding environments, then the analysis is straightforward, but it is hard to consider process and circuit layout interaction when machine or processing conditions change
Solution Approach 1:
The patent implements feedback loops where electrical simulation results are compared with actual silicon measurements through direct probing. The differences between simulated and measured results are used to refine the analysis model and improve subsequent hotspot identification. This feedback mechanism enables the system to adapt to changing process conditions and accurately capture process-circuit-layout interactions.
Solution Approach 2:
The patent creates a detailed electrical simulation model that copies the actual circuit layout and process conditions. This virtual copy allows comprehensive analysis of process-circuit-layout interactions without requiring physical prototypes for each scenario, enabling the system to adapt to different processing conditions through simulation while maintaining manageable complexity.
4Measurement precision
If direct probing and electrical simulation are performed to achieve accurate hotspot identification, then the analysis accuracy is significantly improved, but the manufacturing process becomes more complex
Solution Approach 1:
The manufacturing process is segmented into distinct phases: initial hotspot identification using simple rules, detailed electrical simulation of identified regions, and targeted silicon verification through direct probing. This segmentation achieves high measurement precision by applying complex analysis only where necessary, while keeping the overall manufacturing process manageable through clear phase separation and focused analysis.
Data Source
AI summary
A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.