IC Layout Critical Cell Optimization for Contact Resistance

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Solution Overview

Problem

As semiconductor devices are scaled down, contact resistance and contact capacitance increase, impairing device performance and limiting further scaling, as conventional layout designs do not consider these factors.

Innovation Solution

The method involves selecting and altering critical cells within integrated circuit design layouts to reduce contact resistance and capacitance by employing low parasitic cells and filler cells, which are mapped into a chip area map to optimize cell spacings and configurations, thereby improving overall circuit performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device sizes and dimensions are reduced to increase density, then device density and cost savings are improved, but contact resistance and contact capacitance increase, degrading device performance

Engineering Contradiction:

Improvedevice densityVSAvoiddevice performance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by differentiating between critical and non-critical cells in the layout. Critical cells that impact performance are selectively modified to reduce contact resistance and capacitance, while non-critical cells use standard designs. This localized optimization allows high device density overall while maintaining performance in critical areas.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters of critical cells, specifically increasing contact spacing and adjusting contact dimensions in selected cells. These parameter modifications reduce parasitic effects (contact resistance and capacitance) in critical paths while maintaining overall device density through efficient layout arrangement.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If conventional layout design is used without considering contact resistance and capacitance, then layout simplicity and fabrication ease are maintained, but device performance deteriorates due to increased parasitic effects

Engineering Contradiction:

Improvelayout simplicityVSAvoiddevice performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the layout into critical and non-critical cells based on their impact on device performance. This segmentation allows conventional layout methods to be used for non-critical cells while applying optimized designs only where necessary, maintaining overall layout simplicity while improving performance in critical areas.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary identification and classification of critical cells during the layout design phase, before final fabrication. This preliminary action allows performance-critical areas to be pre-selected and optimized with appropriate contact spacing and dimensions, ensuring performance requirements are met before manufacturing begins.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8112737B2Contact resistance and capacitance for semiconductor devices

Publication Date: 2012.02.07 TEXAS INSTRUMENTS INC

AI summary

A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.