IC Layout Cut Pattern and Jog Rule for Sub-45nm Spacing
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Solution Overview
Problem
Current optical proximity correction (OPC) techniques fail to provide sufficient fidelity and rules for correcting issues in sub-45 nm integrated circuit designs, leading to inadequate spacing between device features, which can result in deteriorated device performance such as voltage breakdown.
Innovation Solution
An IC design method that employs a cut pattern and jog rule to control the spacing between interconnects by shortening or extending patterns, ensuring sufficient device performance and process window, using a flowchart process to determine the necessity of these adjustments based on predetermined spacing values and performance tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current OPC techniques are used for sub-45 nm designs, then the design can be manufactured with existing tools, but the spacing between device features is insufficient leading to poor device performance
Solution Approach 1:
The patent applies preliminary action by introducing cut patterns and jog extensions to the layout design before manufacturing. These patterns pre-adjust the spacing between interconnects to account for manufacturing variations, ensuring that the final fabricated device achieves adequate spacing and performance without requiring post-manufacturing adjustments.
Solution Approach 2:
The patent changes geometric parameters of the layout by introducing cut patterns (removing material) and jog extensions (adding material) to modify the spacing between interconnects. These parameter adjustments compensate for optical proximity effects and ensure adequate spacing in the final manufactured device, directly addressing the insufficient spacing problem of conventional OPC techniques.
2Productivity
If scaling down continues to smaller technology nodes, then production efficiency increases and costs decrease, but processing and manufacturing complexity increases
Solution Approach 1:
The patent segments the layout modification process into distinct operations: identifying interconnects requiring adjustment, applying cut patterns at specific locations, and adding jog extensions where needed. This segmentation allows complex spacing corrections to be systematically applied across the entire chip design, managing the increasing complexity of sub-45 nm manufacturing while maintaining productivity benefits.
3Adaptability or versatility
If similar designs are scaled down to smaller feature sizes, then the design can be reused without redesign, but the device features become poorly shaped or poorly arranged
Solution Approach 1:
The patent applies local quality by selectively applying cut patterns and jog extensions only to specific interconnects that require spacing adjustment, rather than uniformly modifying the entire design. This localized approach preserves the overall design reusability and scalability while correcting local spacing issues that arise from optical proximity effects at smaller feature sizes.
Data Source
AI summary
An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.