IC Layout Decomposition Minimizing Geometry Splits
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Solution Overview
Problem
Current photolithographic processes face limitations in increasing feature density due to physical constraints such as wavelength and aperture limitations, leading to manufacturing defects like misalignment and errors in decomposing single geometries across multiple exposures, and existing decomposition tools are inefficient in handling repeated polygonal patterns.
Innovation Solution
A method for decomposing an IC design layout into multiple mask layouts by minimizing splits through an objective function optimization, where geometries are assigned to mask layouts without splitting those that can be printed as whole units, and split only when necessary, using segment and shape graphs to identify critical portions and associations, and traversing the solution space to find an optimal decomposition solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processes use conventional single exposure, then manufacturing is simpler, but feature density cannot be increased beyond pitch constraints
Solution Approach 1:
The patent applies segmentation by dividing the design layout into multiple mask layouts (first, second, and third mask layouts) that can be printed separately and then combined. This allows features that would otherwise be too dense for single-exposure photolithography to be manufactured by splitting them across multiple exposures with different pitch requirements, thereby increasing feature density while managing process complexity through systematic decomposition
Solution Approach 2:
The patent introduces a temporal dimension by using multiple sequential exposures instead of a single exposure. The design layout is decomposed into multiple mask layouts that are printed at different times and then merged, effectively adding a time-based dimension to the manufacturing process to overcome the spatial pitch limitations of conventional single-exposure photolithography
2Manufacturing precision
If decomposition tools split geometries across multiple exposures, then feature density increases, but manufacturing defects like misalignment increase
Solution Approach 1:
The patent applies preliminary action by pre-defining merge regions in the mask layouts before the actual printing and merging process. These merge regions are carefully designed to account for potential misalignment, ensuring that when multiple exposures are combined, the features align correctly and manufacturing defects are minimized
Solution Approach 2:
The patent implements beforehand cushioning by incorporating merge regions that act as buffers or cushioning zones between features from different exposures. These regions are designed to absorb potential misalignment errors, ensuring that even if slight positioning variations occur during multi-exposure printing, the final merged result maintains high alignment accuracy and avoids manufacturing defects
3Productivity
If decomposition tools process each geometry independently, then processing is simpler, but efficiency decreases when handling repeated patterns
Solution Approach 1:
The patent applies merging by combining multiple identical or similar geometries into a single representative geometry for processing. When repeated patterns are detected, the decomposition algorithm processes one instance and automatically applies the same decomposition to all identical geometries, significantly improving processing efficiency while managing algorithm complexity through pattern recognition and batch processing
Solution Approach 2:
The patent implements universality by creating a universal decomposition approach that can handle both unique and repeated geometries through the same algorithmic framework. The system automatically detects whether geometries are repeated and applies the appropriate processing strategy, making the decomposition tool universally applicable to various design layouts with different pattern densities without requiring separate processing paths
Data Source
AI summary
Some embodiments provide a method for decomposing a region of an integrated circuit (“IC”) design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.