IC Layout Feature Extraction Using Deep Learning Segmentation
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Solution Overview
Problem
Current methods for integrated circuit layout feature extraction, such as manual measurement and software calculation of local matrix operations, face limitations in scalability, time consumption, human error, high licensing costs, and inaccuracies due to fixed extraction windows.
Innovation Solution
A deep learning-based method using multi-scale full convolution deep networks for image segmentation and feature extraction, including data preparation, model training, transfer learning, and model fusion, to accurately calculate copper line widths, densities, and perimeters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual measurement method is used for layout feature extraction, then measurement can be performed on layout files, but it is time-consuming and prone to human errors
Solution Approach 1:
The patent replaces manual mechanical measurement operations with an automated deep learning-based image processing system. The system converts layout files to images, uses trained models to automatically extract features, and eliminates human intervention in the measurement process, thereby reducing time consumption while maintaining or improving measurement accuracy.
Solution Approach 2:
The deep learning model performs self-service by automatically identifying and measuring layout features without human assistance. The system autonomously processes layout files, extracts features, and generates measurement results, eliminating the need for manual operation and reducing both time consumption and human error.
2Productivity
If software calculation of local matrix operations is used, then feature extraction can be automated, but expensive licensing fees are required
Solution Approach 1:
The patent employs open-source deep learning frameworks and models that are free to use, replacing expensive commercial EDA tools. The system uses freely available libraries such as TensorFlow or PyTorch for model training and inference, thereby achieving automation capability without incurring licensing costs.
Solution Approach 2:
The system creates a digital copy of the layout file in image format and processes this copy through the deep learning model, rather than requiring access to proprietary EDA software. This copying approach enables automation using free open-source tools, eliminating licensing fees while maintaining productivity.
3Device complexity
If fixed extraction window is used for feature extraction, then calculation is simplified, but displacement issues lead to deviations in extracted copper line widths
Solution Approach 1:
The patent transitions from fixed extraction windows to dynamic, adaptive extraction regions. The deep learning model automatically determines the boundaries of features of interest in each layout file, allowing extraction regions to adapt to the actual geometry and scale of copper lines. This dynamic approach eliminates displacement issues and maintains measurement precision without excessive calculation complexity.
4Measurement precision
If manual measurement method is used, then layout features can be measured, but human errors occur in selecting measurement areas
Solution Approach 1:
The patent replaces human operators with an automated deep learning system that consistently identifies and measures layout features. The trained model reliably selects measurement areas based on learned patterns, eliminating human errors while maintaining measurement precision across different layout files.
Solution Approach 2:
The system incorporates feedback mechanisms during model training, where the model learns from annotated examples of correct feature selections. This feedback loop enables the model to reliably identify measurement areas without human intervention, improving both precision and reliability of feature extraction.
Data Source
AI summary
The application discloses a method and device for feature extraction of integrated circuit layouts and a non-transitory computer readable storage medium thereof. A circuit pattern layout file to be implemented on a semiconductor wafer is obtained from a memory. Data preparation and preprocessing is performed on the circuit pattern layout file. A deep learning model is established and trained. Transfer learning and model fusion are performed on the deep learning model. The deep learning model is used to perform image segmentation and feature extraction on the circuit pattern layout file to extract a plurality of features. Density parameters and total perimeter parameters of the plurality of features are calculated.