Integrated Circuit Layout Adjustment for Poly Density Gradient Mitigation

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Solution Overview

Problem

Existing SPICE methodologies fail to accurately predict the effect of component variations and mismatches on integrated circuit performance, particularly due to poly density gradient effects (DGE) that cause uneven chemical mechanical planarization and rapid thermal annealing, leading to device property variations such as mobility and threshold voltage.

Innovation Solution

The system identifies subsets of circuit components sharing the same matching group and merges them, generating a CAD layer to enclose the merged layouts. Dummy patterns are inserted around the CAD layer, and a guard ring is added to mitigate DGE effects, ensuring accurate prediction and verification of integrated circuit performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If repeated reductions in minimum feature size are implemented to improve integration density, then more components can be integrated into a given area, but poly density gradient effects cause uneven chemical mechanical planarization and rapid thermal annealing, leading to device property variations

Engineering Contradiction:

Improveintegration densityVSAvoiddevice property uniformity

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating different layout patterns in different regions of the integrated circuit. Specifically, it implements dense array layouts in regions requiring high integration density while using spaced-out or dummy patterns in other regions to compensate for poly density gradient effects. This allows the circuit to achieve high overall integration density while maintaining device property uniformity through localized pattern adjustments.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent converts the harmful poly density gradient effects into a beneficial design constraint. By recognizing that density gradients cause manufacturing variations, the design intentionally incorporates spaced-out patterns and dummy structures in specific locations to counteract these effects. This transforms the harmful physical effect into a guide for creating compensatory layout structures that improve overall device matching and performance.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Productivity

If SPICE methodologies are used to predict circuit performance, then circuit simulation can be performed, but they fail to accurately predict the effect of component variations and mismatches

Engineering Contradiction:

Improvecircuit design efficiencyVSAvoidperformance prediction accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing layout optimizations and dummy pattern insertions before final circuit fabrication. The design process proactively addresses poly density gradient effects by pre-adjusting layout patterns and adding compensatory structures, rather than relying on post-fabrication measurements or inaccurate SPICE simulations to detect and correct variations. This preliminary corrective action improves both prediction accuracy and design efficiency.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If dummy patterns and guard rings are added to mitigate DGE effects, then device property variations can be reduced, but layout complexity increases

Engineering Contradiction:

Improvedevice property uniformityVSAvoidlayout structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the dummy pattern and guard ring structures. These elements simultaneously serve as: (1) compensatory structures to mitigate poly density gradient effects, (2) spacing elements to maintain proper design rules, (3) anchoring points for layout alignment, and (4) visual delimiters for verification purposes. By combining multiple functions into single structures, the patent reduces overall layout complexity while maintaining device property uniformity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250148184A1Integrated circuit design flow with layout adjustment

Publication Date: 2025.05.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.