Integrated Circuit Layout DRC Violation Fixing

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Solution Overview

Problem

Designers face significant time and resource challenges in manually fixing Design Rule Check (DRC) violations in integrated circuit designs, particularly with the occurrence of systematic DRC clusters.

Innovation Solution

A machine-learning-driven physical closure framework that extracts features from layout regions with systematic DRC violations, generates aggregated-cluster models, and selects target placement recipes to adjust the layout placement, thereby reducing or eliminating systematic DRC clusters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If manual fixing of DRC violations is performed, then design accuracy is improved, but time consumption and resource usage increase significantly

Engineering Contradiction:

ImproveDRC violation fixing accuracyVSAvoidTime for fixing DRC violations

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The system automatically detects and fixes DRC violations using machine learning models and automated placement adjustment, enabling the design tool to service itself without human intervention. The framework autonomously identifies systematic DRC clusters, generates candidate placement adjustments, evaluates them, and applies fixes, replacing manual designer effort with self-service automation.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces the mechanical manual process of DRC violation fixing with an automated computational system. Machine learning models analyze layout patterns and predict effective placement adjustments, substituting human mechanical inspection and modification with algorithmic detection and correction, thereby eliminating time loss while maintaining fixing accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If automated placement adjustment is applied, then productivity is improved, but manufacturing precision may deteriorate

Engineering Contradiction:

ImproveDesign closure speedVSAvoidLayout placement accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The system incorporates feedback loops where the impact of each placement adjustment is evaluated before application. The machine learning model predicts the effectiveness of candidate adjustments and selects only those expected to reduce DRC violations without creating new issues. This feedback mechanism ensures that automated adjustments maintain manufacturing precision while improving productivity.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The framework performs preliminary analysis and evaluation of placement adjustments before applying them to the final layout. Multiple candidate adjustments are generated and assessed in advance, with the best option selected based on predicted DRC reduction and placement quality metrics. This preliminary action prevents poor-quality adjustments from degrading manufacturing precision.

Inventive Principle:

Principle #10Preliminary action

3Ease of operation

If machine learning models are used for DRC reduction, then ease of operation is improved, but device complexity increases

Engineering Contradiction:

ImproveAutomated DRC fixing easeVSAvoidSystem complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The complex machine learning system is segmented into modular components: feature extraction modules that analyze layout characteristics, modeling modules that learn from training data, evaluation modules that assess candidate adjustments, and application modules that implement fixes. This segmentation makes the overall complex system easier to operate by providing clear, separated functions that can be independently managed and understood.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250156621A1Method and system for generating layout design of integrated circuit

Publication Date: 2025.05.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes generating a routed layout of the integrated circuit, the routed layout including a layout region with a systematic design rule check (DRC) violation; extracting features of a placing layout of the integrated circuit to obtain extracted data; extracting features of the layout region to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by performing a similarity measurement operation on the extracted data and the plurality of aggregated-cluster models; and selecting a target placement recipe from a plurality of placement recipes by performing a gain calculating operation to generate an adjusted routing layout.