IC Layout Dummy Feature Encoding for Pattern Identification
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Solution Overview
Problem
Existing IC layout verification processes struggle to accurately locate specific patterns, especially when they are obscured by identical dummy features, leading to difficulties in identifying defects or deficiencies in semiconductor devices during fabrication.
Innovation Solution
The method involves encoding visual distinctions into dummy features within the IC layout, allowing for quicker and easier pattern identification using SEM images by modifying the size and position of dummy features to create unique anchor and tunable dummy features with specific spatial relationships and parameter deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy features are used to fill the IC layout, then manufacturing completeness and design rules are satisfied, but pattern identification accuracy deteriorates because identical dummy features make it impossible to distinguish specific patterns in SEM images
Solution Approach 1:
The patent applies local quality by making dummy features non-uniform through encoding unique identifiers or visual distinctions in specific locations. Instead of all dummy features being identical, each dummy feature or group of dummy features contains localized variations (such as different sizes, shapes, or patterns) that enable identification of specific regions in SEM images while still fulfilling the manufacturing function of filling layout space and satisfying design rules.
2Productivity
If standard IC layout processes are used, then manufacturing efficiency is maintained, but defect location time increases because identical patterns require exhaustive searching through SEM images
Solution Approach 1:
The patent applies preliminary action by encoding identification information into dummy features during the layout design stage, before manufacturing. This preliminary encoding of unique identifiers or visual distinctions allows for rapid defect location during inspection, as the encoded information is already present in the manufactured device. This eliminates the need for time-consuming exhaustive searches while maintaining manufacturing efficiency, as the encoding process is automated and integrated into the standard IC design workflow.
Data Source
AI summary
A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.