IC Layout Dummy Patterns Prevent OPC Bridging
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Solution Overview
Problem
In integrated circuit (IC) manufacturing, the placement of testlines without isolation patterns can lead to sub-resolution assist feature printing issues and bridging problems during the optical proximity correction (OPC) process, causing image fidelity and peeling issues when testlines are abutting other devices on a mask.
Innovation Solution
The method involves inserting dummy patterns within the main pattern boundary and filling the isolation region with additional dummy patterns, arranged with specific dimensions and spacing to prevent sub-resolution assist features from being inserted during the OPC process, thereby enhancing image fidelity and preventing printing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If testlines are placed without isolation patterns, then manufacturing process is simplified, but sub-resolution assist feature printing issues and bridging problems occur during OPC process
Solution Approach 1:
The patent introduces isolation patterns as intermediary elements between testlines and other devices. These isolation patterns act as mediators that prevent direct interaction and potential bridging between testlines and adjacent structures during the OPC process, thereby maintaining image fidelity without complicating the overall testline placement process
Solution Approach 2:
The patent extracts the problematic interaction between testlines and other devices by introducing dedicated isolation patterns. This separation removes the harmful bridging effect while preserving the functional simplicity of testline placement, effectively isolating the testline region from potential interference sources
2Manufacturing precision
If dummy patterns are inserted to prevent sub-resolution assist feature printing, then image fidelity is improved, but pattern density uniformity becomes challenging
Solution Approach 1:
The patent applies local quality by inserting dummy patterns selectively in specific regions where pattern density is insufficient. Rather than uniformly distributing dummy patterns throughout, the method places them strategically in isolation regions and near testlines where sub-resolution assist feature printing is most likely to occur, thereby maintaining image fidelity while preserving overall pattern density uniformity
Solution Approach 2:
The patent changes the parameter of pattern density by adjusting the distribution and density of dummy patterns in different regions. By modifying the local pattern density parameters in isolation regions and near testlines, the method prevents sub-resolution assist feature printing while maintaining uniformity in critical areas
3Reliability
If isolation region is filled with dummy patterns, then bridging problems are prevented, but device complexity increases
Solution Approach 1:
The patent segments the layout into distinct functional regions: testline areas, isolation regions, and device areas. By dividing the layout this way and applying dummy patterns selectively to isolation regions rather than uniformly across the entire layout, the method prevents bridging while minimizing the increase in overall layout complexity
Data Source
AI summary
A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.