IC Layout Edge Relocation for Multiple Patterning Fidelity
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Solution Overview
Problem
In semiconductor integrated circuit manufacturing, multiple patterning processes are necessary due to the limitations of optical lithography, requiring optimization of multiple masks to achieve balanced performance in patterning fidelity and overlay budget, which is challenging with existing methods.
Innovation Solution
The method involves decomposing a target IC layout into sub-layouts and optimizing the pattern edges through relocation within defined regions of freedom to improve manufacturability, using a process model that considers various manufacturing parameters and performance factors, and employing techniques like optical proximity correction and resolution enhancement techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to manufacture patterns with small critical dimensions, then patterning fidelity is improved, but device complexity increases due to the need to collectively optimize multiple masks
Solution Approach 1:
The patent applies segmentation by dividing the target layout into multiple sub-layouts that can be independently optimized. Each sub-layout is assigned to a separate mask, allowing the complex optimization problem to be broken down into manageable segments while still achieving the overall manufacturing precision goals through coordinated processing of all sub-layouts
Solution Approach 2:
The patent implements preliminary action by performing collective optimization of all sub-layouts before actual mask fabrication. This pre-optimization process determines the best configuration for each sub-layout considering interactions between masks, thereby simplifying the subsequent manufacturing process and reducing complexity during production
2Productivity
If geometry size is decreased to increase functional density, then productivity is improved, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent applies parameter changes by adjusting various manufacturing parameters including illumination conditions, focus settings, and exposure doses during the multiple patterning process. These parameter optimizations enable precise patterning at smaller geometry sizes, maintaining manufacturing precision while achieving higher functional density and production efficiency
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) includes: receiving a target layout of the IC, decomposing the target layout into a plurality of sub-layouts for a multiple patterning process, identifying re-locatable pattern edges in the sub-layouts, and relocating the edges to improve manufacturability of the IC. In an embodiment, relocating the edges includes: choosing an evaluation index based on a target manufacturing process, moving one or more of the edges, calculating a score of manufacturability based on the evaluation index, and repeating the moving and the calculating until the score meets a threshold.