IC Layout Encryption for IP Protection
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Solution Overview
Problem
Advanced and emerging integrated circuit (IC) processes face challenges in reliably printing arbitrary geometric patterns due to complex interactions between neighboring features during patterning, and there is a need for effective protection and integration of intellectual property (IP) blocks without incurring high integration costs or risking performance degradation.
Innovation Solution
A method involving encryption and decryption of IC layout objects using a processor, where IC layout data is converted into a byte array, encrypted with a checking code, and stored as an encryption object on a specified layer, allowing for secure protection and verification of IP blocks while maintaining compatibility with existing design tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IP blocks are protected through encryption and verification methods, then IP security and integration cost-effectiveness are improved, but the complexity of the design flow and integration process increases
Solution Approach 1:
The patent applies preliminary action by performing encryption on the netlist before physical design operations. The netlist is encrypted using a verification-friendly format that allows verification tools to access and verify the IP functionality while the encrypted form protects the actual layout information from being exposed during subsequent design and manufacturing processes.
Solution Approach 2:
The patent introduces an intermediary encrypted netlist format that serves as a bridge between the IP provider and the customer's design flow. This encrypted netlist acts as a mediator that enables verification tools to perform their functions while maintaining security, and allows standard physical design tools to operate without needing to understand or expose the underlying IP layout details.
2Measurement precision
If verification tools access IP netlists for functional verification, then verification accuracy is improved, but IP layout information may be exposed leading to security risks
Solution Approach 1:
The patent applies preliminary action by pre-encrypting the netlist in a verification-friendly format before verification occurs. This allows verification tools to access and analyze the functional behavior of the IP with full accuracy, while the encryption structure ensures that the actual geometric layout information remains protected and cannot be extracted or exposed during the verification process.
Data Source
AI summary
The method, executed by at least one processor of a computer, of an encrypting or a decrypting method for an IC layout is proposed. The encrypting method comprises getting a record of an IC layout object from a database. Data of the IC layout object is appended into a byte array. The byte array is encrypted into a second byte array. Each byte of the second byte array is defined as an encryption value to create multiple encryption values. Finally, an encryption object with multiple encryption values is created on a specified layer.