IC Layout Fill Trimming for Timing Violation Resolution

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Solution Overview

Problem

The existing chemical mechanical polishing (CMP) process for integrated circuits (ICs) is density-sensitive and requires uniform density across IC layers, leading to inefficiencies and errors in identifying critical nets and placing fills, resulting in time-consuming iterations to fix timing violations and potential removal of essential topological features.

Innovation Solution

A method that first places fills in the design layout without considering their impact on timing, then performs timing analysis to identify regions for trimming fills, specifically targeting nets with timing violations, and trims fills within these regions to resolve timing issues while maintaining minimum density requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If fills are placed uniformly across the IC layer to achieve density requirements, then CMP process uniformity is improved, but timing violations occur due to fills being placed near critical nets

Engineering Contradiction:
ImproveCMP process uniformityVSAvoidtiming accuracy
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the IC layer into different regions: critical regions around timing-sensitive nets and non-critical regions. Fills are placed selectively in non-critical regions only, avoiding critical regions. This segmentation allows the system to achieve density requirements in non-critical areas while preventing timing violations near critical nets.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different fill placement strategies to different locations on the IC layer. In critical regions near timing-sensitive nets, no fills are placed. In non-critical regions, fills are placed to achieve uniform density. This local differentiation resolves the contradiction by allowing density uniformity where it doesn't affect timing while avoiding fills in timing-critical areas.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple iterations of fill placement and timing analysis are performed to fix timing violations, then timing accuracy is improved, but processing time increases significantly

Engineering Contradiction:
Improvetiming accuracyVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary identification of critical nets and defines exclusion zones around them before fill placement. By pre-establishing which regions should not receive fills, the system avoids the need for multiple iterative corrections. The fill placement is done in a single pass using the pre-defined exclusion zones, significantly reducing processing time while maintaining timing accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses timing analysis feedback to identify critical nets and their impact on signal delays. This feedback is used to define exclusion zones where fills should not be placed. The feedback mechanism allows the system to make informed fill placement decisions without requiring multiple iterations, as the exclusion zones are established based on comprehensive timing analysis before fill insertion.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If fills are placed to achieve minimum density requirements, then CMP process effectiveness is improved, but essential topological features may be removed

Engineering Contradiction:
ImproveCMP process effectivenessVSAvoidtopological feature integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the IC layer into critical regions containing essential topological features and non-critical regions. Fills are placed only in non-critical regions to achieve density requirements, while critical regions are protected from fill placement. This segmentation ensures that essential topological features are preserved while still achieving the density uniformity needed for effective CMP processing.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8713507B1Method and apparatus for efficiently inserting fills in an integrated circuit layout
Publication Date: 2014.04.29 CADENCE DESIGN SYST INC
  • US8713507B1 patent drawing
  • US8713507B1 patent drawing
  • US8713507B1 patent drawing

AI summary

A method for efficiently producing a design layout that includes several fills between and around nets of the design layout is described. The method of some embodiments first places a set of fills in the design layout. The method then performs a timing analysis on the design layout to find out the impact of the fills on the timing of the nets. The method identifies a region of the design layout in which to trim a set of fills in order to fix any timing violations of the nets. The method then trims the set of fills in the identified region. In some embodiments, the method employs different trimming strategies for trimming fills around different nets based on the characteristics of the nets.