IC Layout Block Generation for DRC-Free Floorplan Search

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Solution Overview

Problem

Existing integrated circuit (IC) design processes face challenges in efficiently identifying better layouts that address yield and performance concerns, often resulting in design rule violations and suboptimal power, performance, and area (PPA) trade-offs.

Innovation Solution

A method is employed to generate and exhaustively search for all possible layouts of a circuit, ensuring they are DRC-free and LVS-free, by generating layout blocks, mapping them to a floorplan, and combining them into a layout that satisfies design rules, thereby improving the efficiency of the IC design process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing IC design processes are used to generate layouts, then the design process can be completed, but the likelihood of finding optimal layouts that satisfy design rules and achieve good PPA trade-offs is low

Engineering Contradiction:
Improvelikelihood of finding better layoutVSAvoidefficiency of design process
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The layout generation process is segmented into multiple stages: generating layout blocks from circuit components, mapping blocks to floorplan locations, and combining mapped blocks into complete layouts. This segmentation allows exhaustive search of all possible layouts while maintaining manageable process complexity through automated verification at each stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Layout blocks are generated and pre-verified for design rule compliance before being mapped to the final floorplan. This preliminary action ensures that only valid layout components are combined, reducing the need for post-generation corrections and improving overall design reliability.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If design rules are strictly enforced during layout generation, then manufacturability is improved, but the number of valid layouts is reduced

Engineering Contradiction:
Improvedesign rule complianceVSAvoidnumber of valid layouts
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

Layout blocks are generated and verified for design rule compliance before being mapped to the final floorplan. This preliminary action ensures that only valid layout components are combined, reducing the need for post-generation corrections and improving overall design reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system incorporates verification feedback loops that check generated layouts against design rules and LVS specifications. Layouts that fail verification are automatically rejected or require correction, ensuring only manufacturable designs proceed while maintaining comprehensive search of valid solutions.

Inventive Principle:
Principle #23Feedback

3Reliability

If exhaustive search of all possible layouts is performed, then the likelihood of finding optimal layout is maximized, but the time required for design process increases

Engineering Contradiction:
Improvelikelihood of finding better layoutVSAvoiddesign process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The layout generation process is segmented into multiple stages: generating layout blocks from circuit components, mapping blocks to floorplan locations, and combining mapped blocks into complete layouts. This segmentation allows exhaustive search of all possible layouts while maintaining manageable process complexity through automated verification at each stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses automated copying and replication of verified layout blocks to generate complete layouts. By reusing validated layout block templates, the system can exhaustively search for optimal configurations without manually redesigning each layout from scratch, significantly reducing computational time.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20250342301A1Integrated circuit design method, system and computer program product
Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250342301A1 patent drawing
  • US20250342301A1 patent drawing
  • US20250342301A1 patent drawing

AI summary

A system including a processor configured to generate different first block options, each of which satisfies predetermined design rules and is associated with a first layout feature. The processor is further configured to generate different second block options, each of which satisfies the predetermined design rules and is associated with a second layout feature different from the first layout feature. The processor is further configured to generate different layout blocks. Each of the layout blocks satisfies the predetermined design rules, and comprises at least one of the first block options and at least one of the second block options. The processor is further configured to store the different layout blocks, all of which satisfy the predetermined design rules, in at least one library.