IC Layout Generation with Via-Aware Gate Resistance Modeling
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Solution Overview
Problem
Existing methods for modeling gate resistance in integrated circuits (ICs) often underestimate the actual resistance values, leading to inaccuracies in design and manufacturing processes.
Innovation Solution
A method that involves determining a second modeled gate resistance value by positioning gate vias along the gate width and updating the netlist with a resistor to increase the gate resistance, using an AC model to improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional gate resistance modeling methods are used, then the modeling process is simple, but the accuracy of resistance values is insufficient and tends to underestimate actual resistance
Solution Approach 1:
The gate region is divided into multiple segments based on via positions, with each segment having its own resistance calculation. The netlist is updated to include multiple resistor elements representing different gate regions, allowing for more accurate resistance modeling while maintaining manageable complexity through systematic segmentation
Solution Approach 2:
Different resistance values are assigned to different regions of the gate based on local via positions and gate dimensions. The modeling approach applies locally-adapted resistance calculations rather than uniform modeling, improving accuracy by accounting for spatial variations in gate resistance characteristics
2Reliability
If gate via positioning is optimized to improve resistance accuracy, then the compliance with design specifications improves, but the number of layout revisions increases
Solution Approach 1:
The AC model is applied during the design phase to predict gate resistance behavior before manufacturing. By performing preliminary resistance analysis and via positioning optimization in the design stage, the method prevents compliance issues from arising, thereby reducing the need for costly and time-consuming layout revisions during manufacturing
Solution Approach 2:
The modeling method provides feedback on gate resistance values based on via positions and gate dimensions, allowing designers to adjust via placement to achieve target resistance values. This iterative feedback loop enables optimization of resistance accuracy while minimizing revisions by identifying issues early in the design process
Data Source
AI summary
A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.