IC Layout Generation System Constrained by IR Drop and EM Rules
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing current-resistance voltage drop (IR drop) and electro-migration (EM) effects as feature sizes in integrated circuits (ICs) decrease, leading to performance deterioration and potential failure, requiring time-consuming and resource-intensive iterations of extraction-simulation-modification processes to comply with threshold values.
Innovation Solution
Implementing layout rules and a method to generate layouts that constrain voltage drops and current densities by specifying minimum contact numbers, power via counts, and other geometric constraints, using a combination of layout editing tools and simulation to ensure compliance with predetermined threshold values, and deriving these rules from both simulated test-key layouts and actual IC modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but IR drop effects and electro-migration effects increase causing performance deterioration
Solution Approach 1:
The patent applies preliminary action by establishing layout rules before the actual layout generation. These rules, derived from extracted design rules and simulated test-key layouts, pre-determine optimal power line patterns, contact placements, and via configurations that prevent IR drop and EM effects before they occur during IC operation
Solution Approach 2:
The patent changes key layout parameters such as power line width, contact spacing, via diameter, and track geometry to optimize electrical characteristics. By adjusting these parameters within the layout generation process, the system achieves low IR drop and EM effects while maintaining high integration density
2Reliability
If iterative extraction-simulation-modification processes are used to comply with threshold values, then layout reliability is improved, but the process becomes time-consuming and resource-intensive
Solution Approach 1:
The patent performs preliminary extraction of design rules from existing layouts and generates simulated test-key layouts that satisfy threshold requirements before the actual IC layout design. This pre-validation approach ensures compliance without requiring multiple iterative cycles during the main design process
Solution Approach 2:
The patent creates a simplified test-key layout that copies the essential electrical characteristics of the full IC layout but at a reduced scale. This simulation model allows rapid verification of IR drop and EM effects using the same extraction tools, eliminating the need for time-consuming full-chip simulations
Data Source
AI summary
A method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design, the method includes generating a pattern for the layout based on the circuit design, determining, by a processor, if at least one layout rule is violated by including the generated pattern in the layout and modifying the layout if the at least one layout rule is violated. The at least one layout rule includes a constraint on a relationship between a power line pattern and a device pattern in the layout. The at least one layout rule is specified by comparing a predetermined threshold value with one of an estimated voltage drop along a signal path in a second layout different than the layout or an estimated current density on the signal path in the second layout. The constraint includes a minimum number of contacts per device or power vias per device.