IC Layout Grid Conformity Checks During Schematic Design
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Solution Overview
Problem
The manufacturing of integrated circuits (ICs) faces challenges in meeting demand due to temporary throughput issues and downward pressure on costs, particularly in ensuring that layout patterns conform to different lithographic grids, leading to potential gaps and delays in the design and fabrication process.
Innovation Solution
The method involves using an EDA tool to calculate spatial quantities of combined layout patterns during the schematic design stage, ensuring they conform to both finer and coarser grids, and providing warnings to designers to adjust parameters, thereby preventing gaps and streamlining the design and manufacturing cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If layout patterns are designed to conform to finer lithographic grids, then manufacturing precision is improved, but device complexity increases due to multiple grid requirements
Solution Approach 1:
The EDA tool performs preliminary detection during the schematic design stage to identify whether combined layout patterns will conform to coarser lithographic grids. This early detection prevents later redesign cycles by warning designers before layout completion, allowing them to adjust parameters proactively rather than reactively.
Solution Approach 2:
The EDA tool acts as an intermediary between the design intent and manufacturing requirements. It automatically calculates spatial quantities, detects grid conformity issues, and communicates findings to designers, eliminating the need for manual verification and reducing back-and-forth communication between designers and layout engineers.
2Manufacturing precision
If manual verification of layout patterns is performed, then manufacturing precision is improved, but productivity decreases due to repeated revisions
Solution Approach 1:
The EDA tool performs self-service by automatically detecting whether combined layout patterns conform to coarser lithographic grids without requiring manual intervention. The tool calculates spatial quantities, identifies conformity issues, and provides warnings autonomously, freeing designers from time-consuming manual verification tasks.
Solution Approach 2:
The system implements immediate feedback by warning designers during the schematic design stage when layout patterns are likely to fail grid conformity checks. This real-time feedback loop allows designers to correct issues before proceeding to layout, preventing costly revisions later in the manufacturing process.
3Manufacturing precision
If designers are informed of layout issues early, then manufacturing precision is improved, but device complexity increases due to additional detection mechanisms
Solution Approach 1:
The EDA tool merges the detection of layout grid conformity issues with the existing schematic design workflow. By integrating detection capabilities into the design tool itself rather than as a separate system, the patent avoids adding significant complexity while maintaining high manufacturing precision through automated verification.
Data Source
AI summary
A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.