IC Layout Verification Using Homeomorphic Error Detection

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Solution Overview

Problem

Comparing the physical layout of semiconductor integrated circuits (ICs) with reference layouts is challenging due to their complexity and the presence of image defects, making manual and AI-based comparisons inaccurate and difficult to achieve 100% accuracy.

Innovation Solution

Employing homeomorphic error detection to identify and correct topological discrepancies between the physical and reference IC layouts, using topological equivalence and coverage analysis to automate the comparison process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual comparison methods are used to verify IC layouts, then flexibility and adaptability are maintained, but accuracy and productivity are insufficient to achieve 100% detection reliability

Engineering Contradiction:

Improvedetection accuracyVSAvoidverification speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent replaces manual mechanical comparison methods with an automated computer-based system that uses image processing and topological analysis algorithms. The system automatically extracts polygons from layer images, performs homeomorphic error detection, and compares physical IC layouts with reference layouts, eliminating human subjectivity and achieving 100% detection accuracy while significantly increasing verification productivity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary computational layer that processes raw layer images through polygon extraction and topological equivalence analysis before making final comparison decisions. This intermediary processing stage transforms complex image data into simplified topological representations, enabling accurate and efficient error detection that neither manual inspection nor direct image comparison can achieve

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If AI-based comparison methods are employed to increase productivity, then verification speed improves, but accuracy deteriorates due to image defects and complexity

Engineering Contradiction:

Improveverification speedVSAvoiddetection accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent extracts only the essential topological features (polygons representing metal traces, vias, and circuit components) from the complex layer images, separating the critical verification data from distracting image defects and unnecessary details. This extraction process creates a simplified representation that maintains topological accuracy while eliminating the negative effects of image quality issues on AI-based comparison

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transforms the verification problem from direct pixel-based image comparison to topological parameter comparison. By changing the parameter space from raw image pixels to extracted polygon characteristics (vertices, edges, spatial relationships), the system achieves both high productivity through automated processing and high reliability through topological invariance to image defects

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If detailed image analysis is performed to improve measurement precision, then detection accuracy improves, but device complexity and difficulty of detecting errors increase

Engineering Contradiction:

Improvelayout comparison precisionVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the complex verification task into distinct modular stages: layer image acquisition, polygon extraction, topological equivalence analysis, and error detection. Each stage processes specific aspects of the verification problem independently, reducing overall system complexity while maintaining high measurement precision through specialized processing at each stage

Inventive Principle:

Principle #1Segmentation

4Reliability

If comprehensive quality control checks are performed on all IC batches, then reliability improves, but loss of time and productivity decrease

Engineering Contradiction:

Improvequality control reliabilityVSAvoidverification time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces time-consuming manual quality control inspection with automated computer-based analysis that processes layer images and performs topological comparison instantaneously. The system can verify entire IC batches in minutes rather than hours or days of manual inspection, eliminating the trade-off between comprehensive quality control and time loss

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12524869B2System and method for verification and validation of integrated circuit

Publication Date: 2026.01.13 BATTELLE MEMORIAL INST

AI summary

In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.