Geometry-Based Electrical Hotspot Detection in IC Layouts
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Solution Overview
Problem
Current integrated circuit design techniques fail to effectively detect and address electrical hotspots caused by undesired dopant diffusion, which can affect transistor performance and yield, especially in scaled designs where traditional geometric-based design rules are insufficient.
Innovation Solution
A geometry-based electrical hotspot detection method that calculates a critical path distance between geometric features to identify potential electrical hotspots, independent of geometric-based ground rules, and modifies the layout to eliminate design violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional geometric-based design rules are used to determine manufacturability, then the design process is simple and fast, but electrical hotspots caused by dopant diffusion cannot be detected
Solution Approach 1:
The patent introduces an intermediary computational layer between geometric design rules and electrical property assessment. This intermediary calculates critical path distances through dopant diffusion simulations, acting as a mediator that translates geometric layouts into electrical property predictions without requiring full-scale complex simulations for every design iteration.
Solution Approach 2:
The detection process is segmented into distinct stages: geometric feature extraction, critical path identification, dopant diffusion simulation, and electrical property assessment. This segmentation allows each stage to be optimized independently, reducing overall computational complexity while maintaining detection accuracy.
2Reliability
If full lithography simulations are performed on entire IC layouts, then electrical hotspots can be detected, but the computational time and resources required are excessive
Solution Approach 1:
The patent extracts only the critical regions and paths from the full IC layout that are most susceptible to dopant diffusion effects. By identifying and isolating these critical paths between geometric features, the method performs simulations only on relevant portions rather than the entire layout, dramatically reducing computational time while maintaining detection accuracy.
Solution Approach 2:
Instead of performing complete lithography simulations on entire layouts, the method applies partial simulations focused specifically on critical path regions. This partial action approach performs simulations only where necessary to detect electrical hotspots, avoiding excessive computational resources on non-critical areas.
3Area of moving object
If design features are scaled below the wavelength of the patterning light source, then device density increases, but more of the layout must be examined to determine manufacturability
Solution Approach 1:
The patent performs preliminary identification of critical paths and dopant diffusion susceptibility analysis before full manufacturability assessment. By pre-identifying regions with high diffusion risk based on geometric feature relationships, the method prepares targeted examination regions in advance, reducing the complexity of examining scaled layouts while maintaining comprehensive coverage of critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturability of integrated circuits by accurately detecting and mitigating electrical hotspots, improving device yield and performance by focusing on critical path distances rather than just direct spacing, thereby addressing the limitations of traditional design rules.
Implementation Method 1
Optical lithography or photolithography is a well-known process for transferring geometric shapes onto the surface on a semiconductor wafer. When the light from the light source is directed onto the mask, the light is focused to generate a reduced mask image on the wafer
Implementation Method 2
The light passes through the clear regions of the mask to expose the underlying photoresist layer
Implementation Method 3
The exposed photoresist layer is then developed, typically through chemical removal of the exposed or unexposed regions of the photoresist layer
Data Source
AI summary
A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.