IC Layout Hash Matching for CMP Hotspot Prediction
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Solution Overview
Problem
The existing manufacturing processes for integrated circuits are inefficient in detecting and addressing topology hotspots, which can lead to defects such as recesses or humps during the Chemical Mechanical Polish (CMP) process, resulting in production yield loss and requiring lengthy defect identification and correction cycles.
Innovation Solution
A method is developed to predict hotspots in integrated circuit manufacturing by generating hash values from cropped images of wafer layouts, grouping similar hash values, constructing a hotspot library, and selecting optimal CMP recipes to minimize hotspot occurrence, allowing for pre-emptive hotspot prevention without physical wafer processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical wafer processing and measurement are performed to detect topology hotspots, then defect detection accuracy is improved, but manufacturing cycle time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing hotspot prediction through hash value comparison before actual CMP processing. The system pre-identifies potential hotspot locations by comparing layout hash values against a pre-built hotspot library, allowing defects to be predicted and prevented before physical wafer processing begins, thus eliminating the need for lengthy post-processing measurement cycles
Solution Approach 2:
The patent uses copying by creating hash value representations of the wafer layout and comparing these digital copies against a hotspot library. Instead of physically processing and measuring actual wafers to detect hotspots, the system works with copied representations (hash values) that can be rapidly compared and analyzed, significantly reducing detection time while maintaining accuracy
2Ease of manufacture
If traditional CMP processing is performed without hotspot prediction, then manufacturing simplicity is maintained, but production yield decreases due to undetected defects
Solution Approach 1:
The system performs preliminary hotspot prediction by comparing layout hash values against a pre-construction hotspot library before CMP processing. This early detection mechanism identifies potential defects in advance, allowing manufacturers to adjust processing parameters or select alternative recipes to avoid hotspots, thereby improving production yield without significantly complicating the manufacturing workflow
Solution Approach 2:
The patent introduces an intermediary mechanism (hash value comparison system) that bridges layout design and CMP processing. The hotspot library acts as an intermediary database that mediates between the layout configuration and the actual manufacturing process, providing defect prediction information that guides processing decisions and improves yield without directly interfering with the core manufacturing operations
Data Source
AI summary
A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.